modules/*/wb_acq_core/*: reset datamover at each new acquisition

This is safer as we could have some "old" data fro a previous acquisition in the AXI datamover or AXI interconnect buffers. This would concatenate with the new data.

modules//wb_acq_core/: reset datamover at each new acquisition
This is safer as we could have some "old" data fro a previous acquisition in the AXI datamover or AXI interconnect buffers. This would concatenate with the new data.
5a40fcd2 · Lucas Russo · 8a9adf60 · 5a40fcd2
Commit 5a40fcd2 authored Jun 09, 2017 by Lucas Russo
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acq_ddr3_axis_write.vhd hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_axis_write.vhd +1 -1

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--- a/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_axis_write.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_axis_write.vhd
@@ -916,7 +916,7 @@ begin
          ddr_axis_rstn <= '1';
          ddr_axis_halt <= '0';

-          if ext_rst_n_i = '0' then
+          if ext_rst_n_i = '0' or wr_start_i = '1' then
            hrst_state <= HALT_GEN;
          end if;