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Commit 5ff1949c authored by Lucas Russo's avatar Lucas Russo
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hdl/modules/*/wb_acq_core: remove large buffer FFs 

Now, we implement the same functionality with a simple
sync FIFO, instead with large FFs (up to 1024 bits)
in the current design.

This fixes #40 github issue.
parent 69339f99
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hdl/modules/dbe_wishbone/wb_acq_core/acq_core_pkg.vhd
View file @ 5ff1949c
...@@ -15,6 +15,7 @@ package acq_core_pkg is ...@@ -15,6 +15,7 @@ package acq_core_pkg is
constant c_addr_width : natural := 32; constant c_addr_width : natural := 32;
constant c_chan_id_width : natural := 5; constant c_chan_id_width : natural := 5;
constant c_data_valid_width : natural := 1;
constant c_data_oob_width : natural := 2; -- SOF and EOF constant c_data_oob_width : natural := 2; -- SOF and EOF
constant c_data_oob_sof_ofs : natural := 1; -- SOF offset constant c_data_oob_sof_ofs : natural := 1; -- SOF offset
...@@ -316,10 +317,24 @@ package acq_core_pkg is ...@@ -316,10 +317,24 @@ package acq_core_pkg is
( (
g_data_width : natural := 64; g_data_width : natural := 64;
g_size : natural := 64; g_size : natural := 64;
g_with_wr_count : boolean := false;
g_with_rd_empty : boolean := true;
g_with_rd_full : boolean := false;
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false; g_with_rd_count : boolean := false;
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_with_fifo_inferred : boolean := false;
g_almost_empty_threshold : integer;
g_almost_full_threshold : integer; g_almost_full_threshold : integer;
g_almost_empty_threshold : integer g_async : boolean := true
); );
port port
( (
...@@ -331,6 +346,8 @@ package acq_core_pkg is ...@@ -331,6 +346,8 @@ package acq_core_pkg is
wr_en_i : in std_logic; wr_en_i : in std_logic;
wr_full_o : out std_logic; wr_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0); wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
-- Read clock -- Read clock
rd_clk_i : in std_logic; rd_clk_i : in std_logic;
...@@ -338,9 +355,11 @@ package acq_core_pkg is ...@@ -338,9 +355,11 @@ package acq_core_pkg is
rd_data_o : out std_logic_vector(g_data_width-1 downto 0); rd_data_o : out std_logic_vector(g_data_width-1 downto 0);
rd_valid_o : out std_logic; rd_valid_o : out std_logic;
rd_en_i : in std_logic; rd_en_i : in std_logic;
rd_empty_o : out std_logic; rd_empty_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0) rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic
); );
end component; end component;
...@@ -350,6 +369,7 @@ package acq_core_pkg is ...@@ -350,6 +369,7 @@ package acq_core_pkg is
g_data_width : natural := 64; g_data_width : natural := 64;
g_pkt_size_width : natural := 32; g_pkt_size_width : natural := 32;
g_addr_width : natural := 32; g_addr_width : natural := 32;
g_with_fifo_inferred : boolean := false;
g_pipe_size : natural := 4 g_pipe_size : natural := 4
); );
port port
...@@ -412,6 +432,7 @@ package acq_core_pkg is ...@@ -412,6 +432,7 @@ package acq_core_pkg is
( (
g_acq_num_channels : natural := 1; g_acq_num_channels : natural := 1;
g_acq_channels : t_acq_chan_param_array; g_acq_channels : t_acq_chan_param_array;
g_fc_pipe_size : natural := 4;
-- Do not modify these! As they are dependent of the memory controller generated! -- Do not modify these! As they are dependent of the memory controller generated!
g_ddr_payload_width : natural := 256; -- be careful changing these! g_ddr_payload_width : natural := 256; -- be careful changing these!
g_ddr_dq_width : natural := 64; -- be careful changing these! g_ddr_dq_width : natural := 64; -- be careful changing these!
......
hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd
View file @ 5ff1949c
...@@ -45,6 +45,7 @@ generic ...@@ -45,6 +45,7 @@ generic
( (
g_acq_num_channels : natural := 1; g_acq_num_channels : natural := 1;
g_acq_channels : t_acq_chan_param_array; g_acq_channels : t_acq_chan_param_array;
g_fc_pipe_size : natural := 4;
-- Do not modify these! As they are dependent of the memory controller generated! -- Do not modify these! As they are dependent of the memory controller generated!
g_ddr_payload_width : natural := 256; -- be careful changing these! g_ddr_payload_width : natural := 256; -- be careful changing these!
g_ddr_dq_width : natural := 64; -- be careful changing these! g_ddr_dq_width : natural := 64; -- be careful changing these!
...@@ -126,7 +127,7 @@ architecture rtl of acq_ddr3_iface is ...@@ -126,7 +127,7 @@ architecture rtl of acq_ddr3_iface is
-- Flow Control constants -- Flow Control constants
constant c_pkt_size_width : natural := 32; constant c_pkt_size_width : natural := 32;
constant c_pipe_size : natural := 4; ---------constant c_pipe_size : natural := 4;
constant c_addr_cnt_width : natural := c_max_ddr_payload_ratio_log2; constant c_addr_cnt_width : natural := c_max_ddr_payload_ratio_log2;
-- UI Commands -- UI Commands
...@@ -398,10 +399,11 @@ begin ...@@ -398,10 +399,11 @@ begin
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
cmp_fc_source_app : fc_source cmp_fc_source_app : fc_source
generic map ( generic map (
g_data_width => 1, g_data_width => 1, -- Dummy value
g_pkt_size_width => c_pkt_size_width, g_pkt_size_width => c_pkt_size_width,
g_addr_width => g_ddr_addr_width, g_addr_width => g_ddr_addr_width,
g_pipe_size => c_pipe_size g_with_fifo_inferred => true,
g_pipe_size => g_fc_pipe_size
) )
port map ( port map (
clk_i => ext_clk_i, clk_i => ext_clk_i,
...@@ -441,7 +443,8 @@ begin ...@@ -441,7 +443,8 @@ begin
g_data_width => g_ddr_payload_width + c_ddr_mask_width, g_data_width => g_ddr_payload_width + c_ddr_mask_width,
g_pkt_size_width => c_pkt_size_width, g_pkt_size_width => c_pkt_size_width,
g_addr_width => 1, -- Dummy value g_addr_width => 1, -- Dummy value
g_pipe_size => c_pipe_size g_with_fifo_inferred => true,
g_pipe_size => g_fc_pipe_size
) )
port map ( port map (
clk_i => ext_clk_i, clk_i => ext_clk_i,
......
hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd
View file @ 5ff1949c
...@@ -135,8 +135,6 @@ architecture rtl of acq_fc_fifo is ...@@ -135,8 +135,6 @@ architecture rtl of acq_fc_fifo is
subtype t_fc_addr is std_logic_vector(g_addr_width-1 downto 0); subtype t_fc_addr is std_logic_vector(g_addr_width-1 downto 0);
-- Constants -- Constants
constant c_pipe_size : natural := 4;
constant c_narrowest_channel_width : natural := f_acq_chan_find_narrowest(g_acq_channels); constant c_narrowest_channel_width : natural := f_acq_chan_find_narrowest(g_acq_channels);
constant c_widest_channel_width : natural := f_acq_chan_find_widest(g_acq_channels); constant c_widest_channel_width : natural := f_acq_chan_find_widest(g_acq_channels);
...@@ -690,7 +688,7 @@ begin ...@@ -690,7 +688,7 @@ begin
g_data_width => g_data_out_width, g_data_width => g_data_out_width,
g_pkt_size_width => c_pkt_size_width, g_pkt_size_width => c_pkt_size_width,
g_addr_width => g_addr_width, g_addr_width => g_addr_width,
g_pipe_size => c_pipe_size g_pipe_size => g_fc_pipe_size
) )
port map ( port map (
clk_i => ext_clk_i, clk_i => ext_clk_i,
......
hdl/modules/dbe_wishbone/wb_acq_core/acq_fwft_fifo.vhd
View file @ 5ff1949c
...@@ -34,10 +34,24 @@ generic ...@@ -34,10 +34,24 @@ generic
( (
g_data_width : natural := 64; g_data_width : natural := 64;
g_size : natural := 64; g_size : natural := 64;
g_with_wr_count : boolean := false;
g_with_rd_empty : boolean := true;
g_with_rd_full : boolean := false;
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false; g_with_rd_count : boolean := false;
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_with_fifo_inferred : boolean := false;
g_almost_empty_threshold : integer;
g_almost_full_threshold : integer; g_almost_full_threshold : integer;
g_almost_empty_threshold : integer g_async : boolean := true
); );
port port
( (
...@@ -49,6 +63,8 @@ port ...@@ -49,6 +63,8 @@ port
wr_en_i : in std_logic; wr_en_i : in std_logic;
wr_full_o : out std_logic; wr_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0); wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
-- Read clock -- Read clock
rd_clk_i : in std_logic; rd_clk_i : in std_logic;
...@@ -58,7 +74,9 @@ port ...@@ -58,7 +74,9 @@ port
rd_valid_o : out std_logic; rd_valid_o : out std_logic;
rd_en_i : in std_logic; rd_en_i : in std_logic;
rd_empty_o : out std_logic; rd_empty_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0) rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic
); );
end acq_fwft_fifo; end acq_fwft_fifo;
...@@ -69,33 +87,102 @@ architecture rtl of acq_fwft_fifo is ...@@ -69,33 +87,102 @@ architecture rtl of acq_fwft_fifo is
signal fwft_rd_valid : std_logic; signal fwft_rd_valid : std_logic;
signal fwft_rd_empty : std_logic; signal fwft_rd_empty : std_logic;
signal fifo_count_int : std_logic_vector(f_log2_size(g_size)-1 downto 0);
signal fifo_almost_empty_int : std_logic;
signal fifo_almost_full_int : std_logic;
begin begin
cmp_fwft_async_fifo : generic_async_fifo gen_async_fifo : if (g_async) generate
generic map ( cmp_fwft_async_fifo : generic_async_fifo
g_data_width => g_data_width, generic map (
g_size => g_size, g_data_width => g_data_width,
g_almost_empty_threshold => g_almost_empty_threshold, g_size => g_size,
g_almost_full_threshold => g_almost_full_threshold,
g_with_wr_count => g_with_wr_count, g_with_rd_empty => g_with_rd_empty,
g_with_rd_count => g_with_rd_count g_with_rd_full => g_with_rd_full,
) g_with_rd_almost_empty => g_with_rd_almost_empty,
port map( g_with_rd_almost_full => g_with_rd_almost_full,
rst_n_i => wr_rst_n_i, g_with_rd_count => g_with_rd_count,
clk_wr_i => wr_clk_i, g_with_wr_empty => g_with_wr_empty,
d_i => wr_data_i, g_with_wr_full => g_with_wr_full,
we_i => wr_en_i, g_with_wr_almost_empty => g_with_wr_almost_empty,
wr_count_o => wr_count_o, g_with_wr_almost_full => g_with_wr_almost_full,
g_with_wr_count => g_with_wr_count,
clk_rd_i => rd_clk_i,
q_o => rd_data_o, g_with_fifo_inferred => g_with_fifo_inferred,
rd_i => fwft_rd_en,
rd_count_o => rd_count_o, g_almost_empty_threshold => g_almost_empty_threshold,
g_almost_full_threshold => g_almost_full_threshold
rd_empty_o => fwft_rd_empty, )
wr_full_o => wr_full_o port map(
); rst_n_i => wr_rst_n_i,
clk_wr_i => wr_clk_i,
d_i => wr_data_i,
we_i => wr_en_i,
wr_count_o => wr_count_o,
wr_almost_empty_o => wr_almost_empty_o,
wr_almost_full_o => wr_almost_full_o,
clk_rd_i => rd_clk_i,
q_o => rd_data_o,
rd_i => fwft_rd_en,
rd_count_o => rd_count_o,
rd_almost_empty_o => rd_almost_empty_o,
rd_almost_full_o => rd_almost_full_o,
rd_empty_o => fwft_rd_empty,
wr_full_o => wr_full_o
);
end generate;
gen_sync_fifo : if (not g_async) generate
cmp_fwft_sync_fifo : generic_sync_fifo
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_empty => g_with_rd_empty or g_with_wr_empty,
g_with_full => g_with_rd_full or g_with_wr_full,
g_with_almost_empty => g_with_rd_almost_empty or g_with_wr_almost_empty,
g_with_almost_full => g_with_rd_almost_full or g_with_wr_almost_full,
g_with_count => g_with_rd_count or g_with_wr_count,
g_with_fifo_inferred => g_with_fifo_inferred,
g_almost_empty_threshold => g_almost_empty_threshold,
g_almost_full_threshold => g_almost_full_threshold
)
port map(
rst_n_i => wr_rst_n_i,
clk_i => wr_clk_i,
d_i => wr_data_i,
we_i => wr_en_i,
count_o => fifo_count_int,
q_o => rd_data_o,
rd_i => fwft_rd_en,
empty_o => fwft_rd_empty,
full_o => wr_full_o,
almost_empty_o => fifo_almost_empty_int,
almost_full_o => fifo_almost_full_int
);
wr_count_o <= fifo_count_int;
rd_count_o <= fifo_count_int;
wr_almost_empty_o <= fifo_almost_empty_int;
rd_almost_empty_o <= fifo_almost_empty_int;
wr_almost_full_o <= fifo_almost_full_int;
rd_almost_full_o <= fifo_almost_full_int;
end generate;
-- First Word Fall Through (FWFT) implementation -- First Word Fall Through (FWFT) implementation
fwft_rd_en <= not(fwft_rd_empty) and (not(fwft_rd_valid) or rd_en_i); fwft_rd_en <= not(fwft_rd_empty) and (not(fwft_rd_valid) or rd_en_i);
...@@ -118,4 +205,7 @@ begin ...@@ -118,4 +205,7 @@ begin
-- This is the actual valid flag for this FIFO -- This is the actual valid flag for this FIFO
rd_valid_o <= fwft_rd_valid; rd_valid_o <= fwft_rd_valid;
-- Output assignments
rd_empty_o <= fwft_rd_empty;
end rtl; end rtl;
hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd
View file @ 5ff1949c
...@@ -164,6 +164,8 @@ architecture rtl of wb_acq_core is ...@@ -164,6 +164,8 @@ architecture rtl of wb_acq_core is
constant c_acq_data_width : natural := constant c_acq_data_width : natural :=
f_acq_chan_find_widest(c_acq_channels); f_acq_chan_find_widest(c_acq_channels);
constant c_fc_pipe_size : natural := 8;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Types declaration -- Types declaration
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
...@@ -569,7 +571,8 @@ begin ...@@ -569,7 +571,8 @@ begin
g_addr_width => g_ddr_addr_width, g_addr_width => g_ddr_addr_width,
g_acq_num_channels => g_acq_num_channels, g_acq_num_channels => g_acq_num_channels,
g_acq_channels => g_acq_channels, g_acq_channels => g_acq_channels,
g_fifo_size => g_fifo_fc_size g_fifo_size => g_fifo_fc_size,
g_fc_pipe_size => c_fc_pipe_size
) )
port map port map
( (
...@@ -691,6 +694,7 @@ begin ...@@ -691,6 +694,7 @@ begin
( (
g_acq_num_channels => g_acq_num_channels, g_acq_num_channels => g_acq_num_channels,
g_acq_channels => g_acq_channels, g_acq_channels => g_acq_channels,
g_fc_pipe_size => c_fc_pipe_size,
-- Do not modify these! As they are dependent of the memory controller generated! -- Do not modify these! As they are dependent of the memory controller generated!
g_ddr_payload_width => g_ddr_payload_width, g_ddr_payload_width => g_ddr_payload_width,
g_ddr_dq_width => g_ddr_dq_width, g_ddr_dq_width => g_ddr_dq_width,
......
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