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Beam Positoning Monitor - Gateware
Commit 62a845eb authored by Lucas Russo's avatar Lucas Russo
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platform/artix7/*: remove Xilinx libraries from Manifest 

They should be compiled separately, through scripts
such as the one available in
"hdl/testbench/wishbone/wb_acq_core_test/verilog/
artix7/full_tb_mux/questa_compile.sh".

This is only necessary as some of these libraries contains
encrypted files and can't be compiled externally (e.g., modelsim),
giving us a warning: "memory in protected region".
parent d01c6e95
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Showing with 14 additions and 14 deletions
hdl/platform/artix7/afc_v3/axi_datamover_0/Manifest.py
View file @ 62a845eb
......@@ -3,10 +3,10 @@ if (action == "synthesis"):
else:
files = ["axi_datamover_v5_1/hdl/src/vhdl/",
"blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd",
"fifo_generator_v12_0/simulation/",
"lib_cdc_v1_0/hdl/src/vhdl/",
"lib_fifo_v1_0/hdl/src/vhdl/",
"lib_pkg_v1_0/hdl/src/vhdl/",
"lib_srl_fifo_v1_0/hdl/src/vhdl/",
# "blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd",
# "fifo_generator_v12_0/simulation/",
# "lib_cdc_v1_0/hdl/src/vhdl/",
# "lib_fifo_v1_0/hdl/src/vhdl/",
# "lib_pkg_v1_0/hdl/src/vhdl/",
# "lib_srl_fifo_v1_0/hdl/src/vhdl/",
"sim/"]
hdl/platform/artix7/afc_v3/axi_datamover_bpm/Manifest.py
View file @ 62a845eb
......@@ -3,10 +3,10 @@ if (action == "synthesis"):
else:
files = ["axi_datamover_v5_1/hdl/src/vhdl/",
"blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd",
"fifo_generator_v12_0/simulation/",
"lib_cdc_v1_0/hdl/src/vhdl/",
"lib_fifo_v1_0/hdl/src/vhdl/",
"lib_pkg_v1_0/hdl/src/vhdl/",
"lib_srl_fifo_v1_0/hdl/src/vhdl/",
# "blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd",
# "fifo_generator_v12_0/simulation/",
# "lib_cdc_v1_0/hdl/src/vhdl/",
# "lib_fifo_v1_0/hdl/src/vhdl/",
# "lib_pkg_v1_0/hdl/src/vhdl/",
# "lib_srl_fifo_v1_0/hdl/src/vhdl/",
"sim/"]
hdl/platform/artix7/afc_v3/axi_interconnect/Manifest.py
View file @ 62a845eb
......@@ -3,6 +3,6 @@ if (action == "synthesis"):
else:
files = ["axi_interconnect_v1_7/hdl/verilog/",
"blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd",
# "blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd",
"fifo_generator_v12_0/simulation/",
"sim/"]
hdl/platform/artix7/afc_v3/axi_interconnect_bpm/Manifest.py
View file @ 62a845eb
......@@ -3,6 +3,6 @@ if (action == "synthesis"):
else:
files = ["axi_interconnect_v1_7/hdl/verilog/",
"blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd",
# "blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd",
"fifo_generator_v12_0/simulation/",
"sim/"]
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