hdl/testbench/*/wb_acq_core_test/*: shorten 200MHz reset delay

The 7 series async FIFO will misbehave if the read clk is asserted at the same cycle as the reset is deasserted, causing the FIFO to become full and the output to become undefined (X's). The difference in the reset delays give sufficient ammount of time for the FIFO to correctly reset itself.

hdl/testbench//wb_acq_core_test/: shorten 200MHz reset delay
The 7 series async FIFO will misbehave if the read clk is asserted at the same cycle as the reset is deasserted, causing the FIFO to become full and the output to become undefined (X's). The difference in the reset delays give sufficient ammount of time for the FIFO to correctly reset itself.
6535f81e · Lucas Russo · ea4c86ba · 6535f81e · 6535f81e
Commit 6535f81e authored Sep 08, 2014 by Lucas Russo
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Showing with 5 additions and 3 deletions

clk_rst.v ...ishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v +1 -1

defines.v ...ishbone/wb_acq_core_test/verilog/artix7/full_tb/defines.v +4 -2

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--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/clk_rst.v
@@ -91,7 +91,7 @@ module clk_rst(
    //repeat (`RST_ADC_DELAY) begin
    //  @(posedge clk_200mhz_o);
    //end
-    repeat (`RST_SYS_DELAY) begin
+    repeat (`RST_200MHZ_DELAY) begin
      @(posedge clk_sys_o);
    end


--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/defines.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/defines.v
@@ -37,8 +37,9 @@
 `define CLK_ADC_PERIOD 8882.00 //ps

 // Reset Delay, in Clock Cycles
-`define RST_SYS_DELAY  500 // 5000//101000 // ??? > 500 us
-`define RST_ADC_DELAY  500 // 5000//101000 // ??? > 500 us
+`define RST_SYS_DELAY  		5000
+`define RST_ADC_DELAY  		5000
+`define RST_200MHZ_DELAY 	1000

 /*******************************
 * DDR3 definitions
@@ -52,3 +53,4 @@
 //`define DDR_CK_WIDTH        1
 //`define DDR_CKE_WIDTH       1
 //`define DDR_ODT_WIDTH       1
+