hdl/testbench/*/*_acq_core_test/*: move virtex6 sim to specific folder

This will allow adding more wb_acq_core simulations more easily and for different FPGA families.

hdl/testbench//_acq_core_test/*: move virtex6 sim to specific folder
This will allow adding more wb_acq_core simulations more easily and for different FPGA families.
65d8c401 · Lucas Russo · 3d65c3df · 3d65c3df · 3d65c3df · 3d65c3df
Commit 65d8c401 authored Sep 08, 2014 by Lucas Russo
19 changed files
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/full_tb/Manifest.py
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/full_tb/Manifest.py
-action = "simulation"
-target = "xilinx"
-
-modules = {"local" : ["../../../../../",
-                    "../../../../../sim/ddr_model",
-                    "../../../../../ip_cores/pcie/ml605/ddr_v6/user_design/"]}
-
-files = ["wb_acq_core_tb.v", "defines.v", "timescale.v",
-			"clk_rst.v"]
-
-vlog_opt = "+incdir+../../../../../sim/regs +incdir+../../../../../sim +incdir+../../../../../sim/ddr_model"
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/full_tb/wave.do
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/full_tb/wave.do
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/no_arb_tb/wave.do
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/no_arb_tb/wave.do
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/no_arb_tb/wave_compl.do
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/no_arb_tb/wave_compl.do
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/virtex6/full_tb/Makefile
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/virtex6/full_tb/Makefile
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/virtex6/full_tb/Manifest.py
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/virtex6/full_tb/Manifest.py
+action = "simulation"
+target = "xilinx"
+#syn_device = "xc7a200t"
+syn_device = "xc6vlx240t"
+
+modules = {"local" : ["../../../../../../modules/dbe_wishbone",
+                    "../../../../../../modules/dbe_common",
+                    "../../../../../../modules/rffe_top",
+                    "../../../../../../modules/fabric",
+                    "../../../../../../modules/fmc_adc_common",
+                    "../../../../../../modules/pcie",
+                    "../../../../../../ip_cores/general-cores",
+                    "../../../../../../ip_cores/etherbone-core",
+                    "../../../../../../platform/virtex6/chipscope",
+                    "../../../../../../platform/virtex6/ip_cores",
+                    "../../../../../../sim/ddr_model",
+                    "../../../../../../ip_cores/pcie/ml605/ddr_v6/user_design/"]}
+
+files = ["wb_acq_core_tb.v", "defines.v", "timescale.v",
+			"clk_rst.v"]
+
+vlog_opt = "+incdir+../../../../../../sim/regs +incdir+../../../../../../sim +incdir+../../../../../../sim/ddr_model"
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/no_arb_tb/clk_rst.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/no_arb_tb/clk_rst.v
@@ -91,7 +91,7 @@ module clk_rst(
    //repeat (`RST_ADC_DELAY) begin
    //  @(posedge clk_200mhz_o);
    //end
-    repeat (`RST_SYS_DELAY) begin
+    repeat (`RST_200MHZ_DELAY) begin
      @(posedge clk_sys_o);
    end


--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/no_arb_tb/defines.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/no_arb_tb/defines.v
@@ -37,8 +37,9 @@
 `define CLK_ADC_PERIOD 8882.00 //ps

 // Reset Delay, in Clock Cycles
-`define RST_SYS_DELAY  5000 // 5000//101000 // ??? > 500 us
-`define RST_ADC_DELAY  5000 // 5000//101000 // ??? > 500 us
+`define RST_200MHZ_DELAY 5000
+`define RST_SYS_DELAY  10000 // 5000//101000 // ??? > 500 us
+`define RST_ADC_DELAY  10000 // 5000//101000 // ??? > 500 us

 /*******************************
 * DDR3 definitions

--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/no_arb_tb/run.do
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/no_arb_tb/run.do
-vlog wb_acq_core_tb.v +incdir+"." +incdir+../../../../sim +incdir+../../../../sim/regs
+vlog wb_acq_core_tb.v +incdir+"." +incdir+../../../../../../sim +incdir+../../../../../../sim/regs
 -- make -f Makefile
 -- output log file to file "output.log", set siulation resolution to "fs"
 vsim -l output.log -t fs -L unisim work.wb_acq_core_tb -voptargs="+acc"

--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/full_tb/timescale.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/full_tb/timescale.v
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/full_tb/wave_compl.do
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/full_tb/wave_compl.do
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/full_tb/wb_acq_core_tb.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/full_tb/wb_acq_core_tb.v
@@ -388,6 +388,8 @@ module wb_acq_core_tb;
  wb_acq_core_plain #(.g_ddr_addr_width(ADDR_WIDTH),
                    .g_acq_addr_width(ADDR_WIDTH),
                    .g_fifo_fc_size(ACQ_FIFO_SIZE),
+		    .g_ddr_payload_width(256),
+		    .g_ddr_dq_width(64),      
                    //.g_acq_num_channels(5),
                    //.g_acq_channels({c_n_width64, c_n_width128,
                    //                c_n_width128, c_n_width128, c_n_width128}),

--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/no_arb_tb/Manifest.py
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/no_arb_tb/Manifest.py
 action = "simulation"
 target = "xilinx"

-modules = {"local" : ["../../../../../",
-                    "../../../../../sim/ddr_model"]}
+modules = {"local" : ["../../../../../../",
+                    "../../../../../../sim/ddr_model"]}

 files = ["wb_acq_core_tb.v", "defines.v", "timescale.v",
 			"clk_rst.v"]

-vlog_opt = "+incdir+../../../../../sim/regs +incdir+../../../../../sim +incdir+../../../../../sim/ddr_model"
+vlog_opt = "+incdir+../../../../../../sim/regs +incdir+../../../../../../sim +incdir+../../../../../../sim/ddr_model"
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/full_tb/clk_rst.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/full_tb/clk_rst.v
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/full_tb/defines.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/full_tb/defines.v
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/full_tb/run.do
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/full_tb/run.do
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/no_arb_tb/timescale.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/no_arb_tb/timescale.v
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wave_compl.do
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/virtex6/no_arb_tb/wave_compl.do
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/no_arb_tb/wb_acq_core_tb.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/no_arb_tb/wb_acq_core_tb.v