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Commit 6622b248 authored by Lucas Russo's avatar Lucas Russo
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wb_acq_core/*: fix bad indentation problems

parent e0cdb622
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Showing with 157 additions and 157 deletions
hdl/modules/dbe_wishbone/wb_acq_core/acq_core_pkg.vhd
View file @ 6622b248
......@@ -352,15 +352,15 @@ package acq_core_pkg is
fifo_fc_dreq_i : in std_logic;
fifo_fc_stall_i : in std_logic;
dbg_fifo_we_o : out std_logic;
dbg_fifo_wr_count_o : out std_logic_vector(f_log2_size(g_fifo_size)-1 downto 0);
dbg_fifo_re_o : out std_logic;
dbg_fifo_fc_rd_en_o : out std_logic;
dbg_fifo_rd_empty_o : out std_logic;
dbg_fifo_wr_full_o : out std_logic;
dbg_fifo_fc_valid_fwft_o : out std_logic;
dbg_source_pl_dreq_o : out std_logic;
dbg_source_pl_stall_o : out std_logic;
dbg_fifo_we_o : out std_logic;
dbg_fifo_wr_count_o : out std_logic_vector(f_log2_size(g_fifo_size)-1 downto 0);
dbg_fifo_re_o : out std_logic;
dbg_fifo_fc_rd_en_o : out std_logic;
dbg_fifo_rd_empty_o : out std_logic;
dbg_fifo_wr_full_o : out std_logic;
dbg_fifo_fc_valid_fwft_o : out std_logic;
dbg_source_pl_dreq_o : out std_logic;
dbg_source_pl_stall_o : out std_logic;
dbg_pkt_ct_cnt_o : out std_logic_vector(c_pkt_size_width-1 downto 0);
dbg_shots_cnt_o : out std_logic_vector(c_shots_size_width-1 downto 0)
);
......
hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd
View file @ 6622b248
......@@ -498,44 +498,44 @@ begin
port map
(
-- DDR3 external clock
clk_i => ext_clk_i,
rst_n_i => ext_rst_n_i,
clk_i => ext_clk_i,
rst_n_i => ext_rst_n_i,
cnt_all_pkts_ct_done_p_o => open,
cnt_all_trans_done_p_o => cnt_all_trans_done_app_p,
cnt_en_i => acq_app_cnt_en,
cnt_all_pkts_ct_done_p_o => open,
cnt_all_trans_done_p_o => cnt_all_trans_done_app_p,
cnt_en_i => acq_app_cnt_en,
-- Size of the transaction in g_fifo_size bytes
lmt_pkt_size_i => lmt_full_pkt_size_aggd,
lmt_pkt_size_i => lmt_full_pkt_size_aggd,
-- Number of shots in this acquisition
lmt_shots_nb_i => lmt_shots_nb,
lmt_shots_nb_i => lmt_shots_nb,
-- Acquisition limits valid signal. Qualifies lmt_pkt_size_i and lmt_shots_nb_i
lmt_valid_i => lmt_valid,
lmt_valid_i => lmt_valid,
dbg_pkt_ct_cnt_o => dbg_app_pkt_ct_cnt,
dbg_shots_cnt_o => dbg_app_shots_cnt
dbg_pkt_ct_cnt_o => dbg_app_pkt_ct_cnt,
dbg_shots_cnt_o => dbg_app_shots_cnt
);
cmp_acq_cnt_wdf : acq_cnt
port map
(
-- DDR3 external clock
clk_i => ext_clk_i,
rst_n_i => ext_rst_n_i,
clk_i => ext_clk_i,
rst_n_i => ext_rst_n_i,
cnt_all_pkts_ct_done_p_o => open,
cnt_all_trans_done_p_o => cnt_all_trans_done_wdf_p,
cnt_en_i => acq_wdf_cnt_en,
cnt_all_pkts_ct_done_p_o => open,
cnt_all_trans_done_p_o => cnt_all_trans_done_wdf_p,
cnt_en_i => acq_wdf_cnt_en,
-- Size of the transaction in g_fifo_size bytes
lmt_pkt_size_i => lmt_full_pkt_size_aggd,
lmt_pkt_size_i => lmt_full_pkt_size_aggd,
-- Number of shots in this acquisition
lmt_shots_nb_i => lmt_shots_nb,
lmt_shots_nb_i => lmt_shots_nb,
-- Acquisition limits valid signal. Qualifies lmt_pkt_size_i and lmt_shots_nb_i
lmt_valid_i => lmt_valid,
lmt_valid_i => lmt_valid,
dbg_pkt_ct_cnt_o => dbg_wdf_pkt_ct_cnt,
dbg_shots_cnt_o => dbg_wdf_shots_cnt
dbg_pkt_ct_cnt_o => dbg_wdf_pkt_ct_cnt,
dbg_shots_cnt_o => dbg_wdf_shots_cnt
);
-- Wait for the last pulse
......@@ -590,12 +590,12 @@ begin
-----------------------------------------------------------------------------
cmp_fc_source_app : fc_source
generic map (
g_header_in_width => g_ddr_header_width,
g_data_width => 0, -- Dummy value
g_pkt_size_width => c_pkt_size_width,
g_addr_width => g_ddr_addr_width,
g_with_fifo_inferred => true,
g_pipe_size => g_fc_pipe_size
g_header_in_width => g_ddr_header_width,
g_data_width => 0, -- Dummy value
g_pkt_size_width => c_pkt_size_width,
g_addr_width => g_ddr_addr_width,
g_with_fifo_inferred => true,
g_pipe_size => g_fc_pipe_size
)
port map (
clk_i => ext_clk_i,
......@@ -644,12 +644,12 @@ begin
-----------------------------------------------------------------------------
cmp_fc_source_app_wdf : fc_source
generic map (
g_header_in_width => g_ddr_header_width,
g_data_width => g_ddr_payload_width + c_ddr_mask_width,
g_pkt_size_width => c_pkt_size_width,
g_addr_width => 1, -- Dummy value
g_with_fifo_inferred => true,
g_pipe_size => g_fc_pipe_size
g_header_in_width => g_ddr_header_width,
g_data_width => g_ddr_payload_width + c_ddr_mask_width,
g_pkt_size_width => c_pkt_size_width,
g_addr_width => 1, -- Dummy value
g_with_fifo_inferred => true,
g_pipe_size => g_fc_pipe_size
)
port map (
clk_i => ext_clk_i,
......
hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_read.vhd
View file @ 6622b248
......@@ -382,30 +382,30 @@ begin
port map
(
-- DDR3 external clock
clk_i => ext_clk_i,
rst_n_i => ext_rst_n_i,
clk_i => ext_clk_i,
rst_n_i => ext_rst_n_i,
cnt_all_pkts_ct_done_p_o => open,
cnt_all_trans_done_p_o => cnt_all_req_trans_done_p,
cnt_en_i => valid_trans_out,
cnt_all_pkts_ct_done_p_o => open,
cnt_all_trans_done_p_o => cnt_all_req_trans_done_p,
cnt_en_i => valid_trans_out,
-- Size of the transaction in g_fifo_size bytes
lmt_pkt_size_i => lmt_full_pkt_size_aggd,
lmt_pkt_size_i => lmt_full_pkt_size_aggd,
-- Number of shots in this acquisition
lmt_shots_nb_i => lmt_shots_nb,
lmt_shots_nb_i => lmt_shots_nb,
-- Acquisition limits valid signal. Qualifies lmt_pkt_size and lmt_shots_nb
lmt_valid_i => lmt_valid
lmt_valid_i => lmt_valid
);
cmp_cnt_all_req_trans_done : pulse2level
port map
(
clk_i => ext_clk_i,
rst_n_i => ext_rst_n_i,
clk_i => ext_clk_i,
rst_n_i => ext_rst_n_i,
pulse_i => cnt_all_req_trans_done_p,
clr_i => rb_start_i,
level_o => cnt_all_req_trans_done_l
pulse_i => cnt_all_req_trans_done_p,
clr_i => rb_start_i,
level_o => cnt_all_req_trans_done_l
);
-----------------------------------------------------------------------------
......@@ -415,30 +415,30 @@ begin
port map
(
-- DDR3 external clock
clk_i => ext_clk_i,
rst_n_i => ext_rst_n_i,
clk_i => ext_clk_i,
rst_n_i => ext_rst_n_i,
cnt_all_pkts_ct_done_p_o => open,
cnt_all_trans_done_p_o => cnt_all_recv_trans_done_p,
cnt_en_i => ddr_recv_en,
cnt_all_pkts_ct_done_p_o => open,
cnt_all_trans_done_p_o => cnt_all_recv_trans_done_p,
cnt_en_i => ddr_recv_en,
-- Size of the transaction in g_fifo_size bytes
lmt_pkt_size_i => lmt_full_pkt_size_aggd,
lmt_pkt_size_i => lmt_full_pkt_size_aggd,
-- Number of shots in this acquisition
lmt_shots_nb_i => lmt_shots_nb,
lmt_shots_nb_i => lmt_shots_nb,
-- Acquisition limits valid signal. Qualifies lmt_pkt_size_i and lmt_shots_nb
lmt_valid_i => lmt_valid
lmt_valid_i => lmt_valid
);
cmp_cnt_all_recv_trans_done : pulse2level
port map
(
clk_i => ext_clk_i,
rst_n_i => ext_rst_n_i,
clk_i => ext_clk_i,
rst_n_i => ext_rst_n_i,
pulse_i => cnt_all_recv_trans_done_p,
clr_i => rb_start_i,
level_o => cnt_all_recv_trans_done_l
pulse_i => cnt_all_recv_trans_done_p,
clr_i => rb_start_i,
level_o => cnt_all_recv_trans_done_l
);
lmt_all_trans_done_p_o <= cnt_all_recv_trans_done_p;
......
hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd
View file @ 6622b248
......@@ -108,15 +108,15 @@ port
fifo_fc_dreq_i : in std_logic;
fifo_fc_stall_i : in std_logic;
dbg_fifo_we_o : out std_logic;
dbg_fifo_wr_count_o : out std_logic_vector(f_log2_size(g_fifo_size)-1 downto 0);
dbg_fifo_re_o : out std_logic;
dbg_fifo_fc_rd_en_o : out std_logic;
dbg_fifo_rd_empty_o : out std_logic;
dbg_fifo_wr_full_o : out std_logic;
dbg_fifo_fc_valid_fwft_o : out std_logic;
dbg_source_pl_dreq_o : out std_logic;
dbg_source_pl_stall_o : out std_logic;
dbg_fifo_we_o : out std_logic;
dbg_fifo_wr_count_o : out std_logic_vector(f_log2_size(g_fifo_size)-1 downto 0);
dbg_fifo_re_o : out std_logic;
dbg_fifo_fc_rd_en_o : out std_logic;
dbg_fifo_rd_empty_o : out std_logic;
dbg_fifo_wr_full_o : out std_logic;
dbg_fifo_fc_valid_fwft_o : out std_logic;
dbg_source_pl_dreq_o : out std_logic;
dbg_source_pl_stall_o : out std_logic;
dbg_pkt_ct_cnt_o : out std_logic_vector(c_pkt_size_width-1 downto 0);
dbg_shots_cnt_o : out std_logic_vector(c_shots_size_width-1 downto 0)
);
......@@ -489,24 +489,24 @@ begin
port map
(
-- Write clock
wr_clk_i => fs_clk_i,
wr_rst_n_i => fs_rst_n_i,
wr_clk_i => fs_clk_i,
wr_rst_n_i => fs_rst_n_i,
wr_data_i => fifo_fc_id_din,
wr_en_i => fifo_fc_id_we,
wr_data_i => fifo_fc_id_din,
wr_en_i => fifo_fc_id_we,
-- Ignored, as we rely on the data FIFOs wr_full signal
wr_full_o => open,
wr_count_o => open,
wr_full_o => open,
wr_count_o => open,
-- Read clock
rd_clk_i => ext_clk_i,
rd_rst_n_i => ext_rst_n_i,
rd_data_o => fifo_fc_id_dout,
rd_valid_o => fifo_fc_id_valid_out,
rd_en_i => fifo_fc_id_rd_en,
rd_empty_o => open,
rd_count_o => open
rd_clk_i => ext_clk_i,
rd_rst_n_i => ext_rst_n_i,
rd_data_o => fifo_fc_id_dout,
rd_valid_o => fifo_fc_id_valid_out,
rd_en_i => fifo_fc_id_rd_en,
rd_empty_o => open,
rd_count_o => open
);
fifo_fc_id_rd_en <= fifo_fc_rd_en;
......@@ -518,33 +518,33 @@ begin
generic map
(
-- For simplicity take the widest channel
g_data_width => c_widest_channel_width,
g_size => g_fifo_size,
g_almost_empty_threshold => 0,
g_almost_full_threshold => 0,
g_with_wr_count => true,
g_with_rd_count => false
g_data_width => c_widest_channel_width,
g_size => g_fifo_size,
g_almost_empty_threshold => 0,
g_almost_full_threshold => 0,
g_with_wr_count => true,
g_with_rd_count => false
)
port map
(
-- Write clock
wr_clk_i => fs_clk_i,
wr_rst_n_i => fs_rst_n_i,
wr_clk_i => fs_clk_i,
wr_rst_n_i => fs_rst_n_i,
wr_data_i => fifo_fc_din(i),
wr_en_i => fifo_fc_we(i),
wr_full_o => fifo_fc_wr_full(i),
wr_count_o => fifo_fc_wr_count(i),
wr_data_i => fifo_fc_din(i),
wr_en_i => fifo_fc_we(i),
wr_full_o => fifo_fc_wr_full(i),
wr_count_o => fifo_fc_wr_count(i),
-- Read clock
rd_clk_i => ext_clk_i,
rd_rst_n_i => ext_rst_n_i,
rd_data_o => fifo_fc_dout(i),
rd_valid_o => fifo_fc_valid_out(i),
rd_en_i => fifo_fc_rd_en,
rd_empty_o => fifo_fc_rd_empty(i),
rd_count_o => open
rd_clk_i => ext_clk_i,
rd_rst_n_i => ext_rst_n_i,
rd_data_o => fifo_fc_dout(i),
rd_valid_o => fifo_fc_valid_out(i),
rd_en_i => fifo_fc_rd_en,
rd_empty_o => fifo_fc_rd_empty(i),
rd_count_o => open
);
-- Extract fifo trigger from fifo_fc_dout
......@@ -650,7 +650,7 @@ begin
);
rst_trans_ext_sync <= '1' when req_rst_trans_sync = '1' and
fifo_fc_all_trans_done_lvl = '1' else '0';
fifo_fc_all_trans_done_lvl = '1' else '0';
-- Delay Reset signal to Level logic. This will give a few cycles
-- for all modules to safely reset
......@@ -719,22 +719,22 @@ begin
port map
(
-- DDR3 external clock
clk_i => ext_clk_i,
rst_n_i => acq_cnt_rst_n,
clk_i => ext_clk_i,
rst_n_i => acq_cnt_rst_n,
cnt_all_pkts_ct_done_p_o => fifo_pkt_sent_ct_all,
cnt_all_trans_done_p_o => shots_sent_all,
cnt_en_i => acq_cnt_en,
cnt_all_pkts_ct_done_p_o => fifo_pkt_sent_ct_all,
cnt_all_trans_done_p_o => shots_sent_all,
cnt_en_i => acq_cnt_en,
-- Size of the transaction in g_fifo_size bytes
lmt_pkt_size_i => lmt_full_pkt_size_aggd,
lmt_pkt_size_i => lmt_full_pkt_size_aggd,
-- Number of shots in this acquisition
lmt_shots_nb_i => lmt_shots_nb,
lmt_shots_nb_i => lmt_shots_nb,
-- Acquisition limits valid signal. Qualifies lmt_pkt_size_i and lmt_shots_nb_i
lmt_valid_i => lmt_valid_ext,
lmt_valid_i => lmt_valid_ext,
dbg_pkt_ct_cnt_o => dbg_pkt_ct_cnt,
dbg_shots_cnt_o => dbg_shots_cnt
dbg_pkt_ct_cnt_o => dbg_pkt_ct_cnt,
dbg_shots_cnt_o => dbg_shots_cnt
);
dbg_pkt_ct_cnt_o <= dbg_pkt_ct_cnt;
......@@ -764,12 +764,12 @@ begin
cmp_conv_fifo_fc_all_trans_done : pulse2level
port map
(
clk_i => ext_clk_i,
rst_n_i => ext_rst_n_i,
clk_i => ext_clk_i,
rst_n_i => ext_rst_n_i,
pulse_i => fifo_fc_all_trans_done,
clr_i => rst_trans_ext_sync_d,
level_o => fifo_fc_all_trans_done_lvl
pulse_i => fifo_fc_all_trans_done,
clr_i => rst_trans_ext_sync_d,
level_o => fifo_fc_all_trans_done_lvl
);
-----------------------------------------------------------------------------
......
hdl/modules/dbe_wishbone/wb_acq_core/acq_multishot_dpram.vhd
View file @ 6622b248
......@@ -223,4 +223,4 @@ begin
dpram_dout_o <= dpram0_doutb when buffer_sel_i = '1' else dpram1_doutb;
dpram_valid_o <= dpram_valid;
end rtl;
\ No newline at end of file
end rtl;
hdl/modules/dbe_wishbone/wb_acq_core/data_checker.vhd
View file @ 6622b248
......@@ -421,16 +421,16 @@ begin
port map
(
-- DDR3 external clock
clk_i => ext_clk_i,
rst_n_i => ext_rst_n_i,
clk_i => ext_clk_i,
rst_n_i => ext_rst_n_i,
cnt_all_pkts_ct_done_p_o => open,
cnt_all_trans_done_p_o => data_chk_done_p,
cnt_en_i => data_chk_en,
cnt_all_pkts_ct_done_p_o => open,
cnt_all_trans_done_p_o => data_chk_done_p,
cnt_en_i => data_chk_en,
lmt_pkt_size_i => lmt_pkt_size,
lmt_shots_nb_i => lmt_shots_nb,
lmt_valid_i => lmt_valid
lmt_pkt_size_i => lmt_pkt_size,
lmt_shots_nb_i => lmt_shots_nb,
lmt_valid_i => lmt_valid
);
-- Convert from pulse to level signal
......
hdl/modules/dbe_wishbone/wb_acq_core/fc_source.vhd
View file @ 6622b248
......@@ -90,19 +90,19 @@ architecture rtl of fc_source is
subtype t_fc_pkt is unsigned(g_pkt_size_width-1 downto 0);
-- Constants
constant c_pipe_almost_full_thres : natural := g_pipe_size-2;
constant c_pipe_almost_empty_thres : natural := 2;
constant c_pre_out_fifo_width : natural := g_header_in_width + g_data_width + g_addr_width +
c_data_oob_width;
constant c_pre_out_fifo_data_lsb : natural := 0;
constant c_pre_out_fifo_data_msb : natural := c_pre_out_fifo_data_lsb + g_header_in_width + g_data_width - 1;
constant c_pre_out_fifo_addr_lsb : natural := c_pre_out_fifo_data_msb + 1;
constant c_pre_out_fifo_addr_msb : natural := c_pre_out_fifo_addr_lsb + g_addr_width - 1;
constant c_pre_out_fifo_oob_lsb : natural := c_pre_out_fifo_addr_msb + 1;
constant c_pre_out_fifo_oob_msb : natural := c_pre_out_fifo_oob_lsb + c_data_oob_width - 1;
constant c_fc_in_header_top_idx : natural := g_header_in_width+g_data_width-1;
constant c_fc_in_header_bot_idx : natural := g_data_width;
constant c_pipe_almost_full_thres : natural := g_pipe_size-2;
constant c_pipe_almost_empty_thres : natural := 2;
constant c_pre_out_fifo_width : natural := g_header_in_width + g_data_width + g_addr_width +
c_data_oob_width;
constant c_pre_out_fifo_data_lsb : natural := 0;
constant c_pre_out_fifo_data_msb : natural := c_pre_out_fifo_data_lsb + g_header_in_width + g_data_width - 1;
constant c_pre_out_fifo_addr_lsb : natural := c_pre_out_fifo_data_msb + 1;
constant c_pre_out_fifo_addr_msb : natural := c_pre_out_fifo_addr_lsb + g_addr_width - 1;
constant c_pre_out_fifo_oob_lsb : natural := c_pre_out_fifo_addr_msb + 1;
constant c_pre_out_fifo_oob_msb : natural := c_pre_out_fifo_oob_lsb + c_data_oob_width - 1;
constant c_fc_in_header_top_idx : natural := g_header_in_width+g_data_width-1;
constant c_fc_in_header_bot_idx : natural := g_data_width;
-- Signals
signal fc_first_data : std_logic;
......@@ -144,7 +144,7 @@ architecture rtl of fc_source is
signal fc_oob_out_int : t_fc_data_oob;
-- Counters
signal fc_in_pend_cnt : t_fc_pkt;
signal fc_in_pend_cnt : t_fc_pkt;
signal output_pipe_full : std_logic;
signal output_pipe_almost_full : std_logic;
......@@ -323,15 +323,15 @@ begin
end if;
end process;
pl_stall_o <= pl_stall_r;
pl_dreq_o <= pl_dreq_r;
pl_stall_o <= pl_stall_r;
pl_dreq_o <= pl_dreq_r;
fc_dout_o <= fc_data_out_int;
fc_valid_o <= fc_valid_out_int;
fc_addr_o <= fc_addr_out_int;
fc_sof_o <= fc_oob_out_int(c_data_oob_sof_ofs);
fc_eof_o <= fc_oob_out_int(c_data_oob_eof_ofs);
fc_dout_o <= fc_data_out_int;
fc_valid_o <= fc_valid_out_int;
fc_addr_o <= fc_addr_out_int;
fc_sof_o <= fc_oob_out_int(c_data_oob_sof_ofs);
fc_eof_o <= fc_oob_out_int(c_data_oob_eof_ofs);
pl_pkt_sent_o <= pkt_sent;
pl_pkt_sent_o <= pkt_sent;
end rtl;
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