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Beam Positoning Monitor - Gateware
Commit 66d474fd authored by Lucas Russo's avatar Lucas Russo
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various hdl: fix modelsim errors

parent 3b0531d5
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Showing with 20 additions and 13 deletions
hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd
View file @ 66d474fd
......@@ -480,7 +480,7 @@ begin
-- Simulation / Syntesis Only consructs. Is there a better way to do it?
s_data(c_num_adc_data_msb downto 0) <= s_adc_dout(c_num_adc_data_msb downto 0);
s_data(c_wbs_data_width downto c_num_adc_data_msb+1) <= (others => '0');
--s_data(c_wbs_data_width downto c_num_adc_data_msb+1) <= (others => '0');
gen_stream_valid : if (g_sim = 0) generate
s_dvalid <= cdce_pll_status_i and s_mmcm_adc_locked;
......
hdl/modules/dbe_wishbone/wb_stream/xwb_stream_source.vhd
View file @ 66d474fd
......@@ -151,8 +151,8 @@ entity wb_stream_source is
-- Wishbone Fabric Interface I/O
src_dat_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
src_adr_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
src_dat_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
src_adr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
src_sel_o : out std_logic_vector((c_wbs_data_width/8)-1 downto 0);
src_cyc_o : out std_logic;
src_stb_o : out std_logic;
......
hdl/modules/fmc_adc_common/fmc_adc_pkg.vhd
View file @ 66d474fd
......@@ -245,7 +245,7 @@ package fmc_adc_pkg is
return t_chain_intercon;
function f_first_used_clk(use_clk_chain : std_logic_vector)
return natural;
return integer;
function f_explicitly_clk_data_map(map_chain : t_map_clk_data_chain)
return boolean;
......@@ -260,7 +260,7 @@ package fmc_adc_pkg is
function f_with_ref_clk(clk_chain : natural; ref_clk : natural)
return boolean;
function f_num_adc_pins(ddr_data : boolean) return natural;
function f_num_adc_pins(sdr_data : boolean) return natural;
function f_std_logic_to_bool(input : std_logic) return boolean;
......@@ -630,7 +630,7 @@ package body fmc_adc_pkg is
-- Determine first used clock
function f_first_used_clk(use_clk_chain : std_logic_vector)
return natural
return integer
is
begin
for i in 0 to c_num_adc_channels-1 loop
......
hdl/sim/ddr_model/ddr3_model_parameters.vh
View file @ 66d474fd
......@@ -555,7 +555,8 @@
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
`else `define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin
`else
`define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
......@@ -783,7 +784,8 @@
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width**
parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used
`else `define x16
`else
`define x16
parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used
parameter ADDR_BITS = 15; // MAX Address Bits
parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used
......@@ -1505,7 +1507,8 @@
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
`else `define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin
`else
`define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
......@@ -1733,7 +1736,8 @@
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width**
parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used
`else `define x16
`else
`define x16
parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used
parameter ADDR_BITS = 14; // MAX Address Bits
parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used
......@@ -1931,7 +1935,8 @@
endfunction
`else `define x1Gb // 1Gb parts
`else
`define x1Gb // 1Gb parts
// SYMBOL UNITS DESCRIPTION
// ------ ----- -----------
......@@ -2455,7 +2460,8 @@
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
`else `define sg25 // sg25 is equivalent to the JEDEC DDR3-800 (6-6-6) speed bin
`else
`define sg25 // sg25 is equivalent to the JEDEC DDR3-800 (6-6-6) speed bin
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
......@@ -2695,7 +2701,8 @@
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width**
parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used
`else `define x16
`else
`define x16
parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used
parameter ADDR_BITS = 13; // MAX Address Bits
parameter ROW_BITS = 13; // Set this parameter to control how many Address bits are used
......
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