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Beam Positoning Monitor - Gateware
Commit 675376c3 authored by Lucas Russo's avatar Lucas Russo
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dbe_wishbone/*,pcie/*: update Thread ID width signals 

As we changed the Thread ID width, we need to
update it here.
parent 3f5a1a1b
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Showing with 40 additions and 51 deletions
hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd
View file @ 675376c3
......@@ -1447,7 +1447,7 @@ package dbe_wishbone_pkg is
-----------------------------
-- DDR3 SDRAM Interface
-----------------------------
ddr_aximm_ma_awid_o : out std_logic_vector (0 downto 0);
ddr_aximm_ma_awid_o : out std_logic_vector (3 downto 0);
ddr_aximm_ma_awaddr_o : out std_logic_vector (31 downto 0);
ddr_aximm_ma_awlen_o : out std_logic_vector (7 downto 0);
ddr_aximm_ma_awsize_o : out std_logic_vector (2 downto 0);
......@@ -1464,10 +1464,10 @@ package dbe_wishbone_pkg is
ddr_aximm_ma_wvalid_o : out std_logic;
ddr_aximm_ma_wready_i : in std_logic;
ddr_aximm_ma_bready_o : out std_logic;
ddr_aximm_ma_bid_i : in std_logic_vector (0 downto 0);
ddr_aximm_ma_bid_i : in std_logic_vector (3 downto 0);
ddr_aximm_ma_bresp_i : in std_logic_vector (1 downto 0);
ddr_aximm_ma_bvalid_i : in std_logic;
ddr_aximm_ma_arid_o : out std_logic_vector (0 downto 0);
ddr_aximm_ma_arid_o : out std_logic_vector (3 downto 0);
ddr_aximm_ma_araddr_o : out std_logic_vector (31 downto 0);
ddr_aximm_ma_arlen_o : out std_logic_vector (7 downto 0);
ddr_aximm_ma_arsize_o : out std_logic_vector (2 downto 0);
......@@ -1479,7 +1479,7 @@ package dbe_wishbone_pkg is
ddr_aximm_ma_arvalid_o : out std_logic;
ddr_aximm_ma_arready_i : in std_logic;
ddr_aximm_ma_rready_o : out std_logic;
ddr_aximm_ma_rid_i : in std_logic_vector (0 downto 0);
ddr_aximm_ma_rid_i : in std_logic_vector (3 downto 0);
ddr_aximm_ma_rdata_i : in std_logic_vector (g_ddr_payload_width-1 downto 0);
ddr_aximm_ma_rresp_i : in std_logic_vector (1 downto 0);
ddr_aximm_ma_rlast_i : in std_logic;
......@@ -1695,7 +1695,7 @@ package dbe_wishbone_pkg is
-- DDR memory controller interface --
ddr_aximm_sl_aclk_o : out std_logic;
ddr_aximm_sl_aresetn_o : out std_logic;
ddr_aximm_w_sl_awid_i : in std_logic_vector (0 downto 0);
ddr_aximm_w_sl_awid_i : in std_logic_vector (3 downto 0);
ddr_aximm_w_sl_awaddr_i : in std_logic_vector (31 downto 0);
ddr_aximm_w_sl_awlen_i : in std_logic_vector (7 downto 0);
ddr_aximm_w_sl_awsize_i : in std_logic_vector (2 downto 0);
......@@ -1712,10 +1712,10 @@ package dbe_wishbone_pkg is
ddr_aximm_w_sl_wvalid_i : in std_logic;
ddr_aximm_w_sl_wready_o : out std_logic;
ddr_aximm_w_sl_bready_i : in std_logic;
ddr_aximm_w_sl_bid_o : out std_logic_vector (0 downto 0);
ddr_aximm_w_sl_bid_o : out std_logic_vector (3 downto 0);
ddr_aximm_w_sl_bresp_o : out std_logic_vector (1 downto 0);
ddr_aximm_w_sl_bvalid_o : out std_logic;
ddr_aximm_r_sl_arid_i : in std_logic_vector (0 downto 0);
ddr_aximm_r_sl_arid_i : in std_logic_vector (3 downto 0);
ddr_aximm_r_sl_araddr_i : in std_logic_vector (31 downto 0);
ddr_aximm_r_sl_arlen_i : in std_logic_vector (7 downto 0);
ddr_aximm_r_sl_arsize_i : in std_logic_vector (2 downto 0);
......@@ -1727,7 +1727,7 @@ package dbe_wishbone_pkg is
ddr_aximm_r_sl_arvalid_i : in std_logic;
ddr_aximm_r_sl_arready_o : out std_logic;
ddr_aximm_r_sl_rready_i : in std_logic;
ddr_aximm_r_sl_rid_o : out std_logic_vector (0 downto 0 );
ddr_aximm_r_sl_rid_o : out std_logic_vector (3 downto 0 );
ddr_aximm_r_sl_rdata_o : out std_logic_vector (c_ddr_payload_width-1 downto 0);
ddr_aximm_r_sl_rresp_o : out std_logic_vector (1 downto 0 );
ddr_aximm_r_sl_rlast_o : out std_logic;
......
hdl/modules/dbe_wishbone/wb_acq_core_mux/wb_acq_core_mux.vhd
View file @ 675376c3
......@@ -127,7 +127,7 @@ port
-----------------------------
-- DDR3 SDRAM Interface
-----------------------------
ddr_aximm_ma_awid_o : out std_logic_vector (0 downto 0);
ddr_aximm_ma_awid_o : out std_logic_vector (3 downto 0);
ddr_aximm_ma_awaddr_o : out std_logic_vector (31 downto 0);
ddr_aximm_ma_awlen_o : out std_logic_vector (7 downto 0);
ddr_aximm_ma_awsize_o : out std_logic_vector (2 downto 0);
......@@ -144,10 +144,10 @@ port
ddr_aximm_ma_wvalid_o : out std_logic;
ddr_aximm_ma_wready_i : in std_logic;
ddr_aximm_ma_bready_o : out std_logic;
ddr_aximm_ma_bid_i : in std_logic_vector (0 downto 0);
ddr_aximm_ma_bid_i : in std_logic_vector (3 downto 0);
ddr_aximm_ma_bresp_i : in std_logic_vector (1 downto 0);
ddr_aximm_ma_bvalid_i : in std_logic;
ddr_aximm_ma_arid_o : out std_logic_vector (0 downto 0);
ddr_aximm_ma_arid_o : out std_logic_vector (3 downto 0);
ddr_aximm_ma_araddr_o : out std_logic_vector (31 downto 0);
ddr_aximm_ma_arlen_o : out std_logic_vector (7 downto 0);
ddr_aximm_ma_arsize_o : out std_logic_vector (2 downto 0);
......@@ -159,7 +159,7 @@ port
ddr_aximm_ma_arvalid_o : out std_logic;
ddr_aximm_ma_arready_i : in std_logic;
ddr_aximm_ma_rready_o : out std_logic;
ddr_aximm_ma_rid_i : in std_logic_vector (0 downto 0);
ddr_aximm_ma_rid_i : in std_logic_vector (3 downto 0);
ddr_aximm_ma_rdata_i : in std_logic_vector (g_ddr_payload_width-1 downto 0);
ddr_aximm_ma_rresp_i : in std_logic_vector (1 downto 0);
ddr_aximm_ma_rlast_i : in std_logic;
......@@ -206,12 +206,6 @@ architecture rtl of wb_acq_core_mux is
signal axis_s2mm_valid_cnt_array : t_aximm_valid_cnt_array(g_acq_num_cores-1 downto 0);
signal axis_mm2s_valid_cnt_array : t_aximm_valid_cnt_array(g_acq_num_cores-1 downto 0);
-- Intermediate signals
signal ddr_aximm_ma_awid_int : std_logic_vector (3 downto 0);
signal ddr_aximm_ma_bid_int : std_logic_vector (3 downto 0);
signal ddr_aximm_ma_arid_int : std_logic_vector (3 downto 0);
signal ddr_aximm_ma_rid_int : std_logic_vector (3 downto 0);
begin
assert (g_acq_num_cores <= c_num_max_acq_cores)
......@@ -750,7 +744,7 @@ begin
s07_axi_rready => axi_mm2s_r_mo_array(7).rready, -- in std_logic;
m00_axi_areset_out_n => open, -- out std_logic;
m00_axi_aclk => ext_clk_i, -- in std_logic;
m00_axi_awid => ddr_aximm_ma_awid_int, -- out std_logic_vector ( 3 downto 0 );
m00_axi_awid => ddr_aximm_ma_awid_o, -- out std_logic_vector ( 3 downto 0 );
m00_axi_awaddr => ddr_aximm_ma_awaddr_o, -- out std_logic_vector ( 31 downto 0 );
m00_axi_awlen => ddr_aximm_ma_awlen_o, -- out std_logic_vector ( 7 downto 0 );
m00_axi_awsize => ddr_aximm_ma_awsize_o, -- out std_logic_vector ( 2 downto 0 );
......@@ -766,11 +760,11 @@ begin
m00_axi_wlast => ddr_aximm_ma_wlast_o, -- out std_logic;
m00_axi_wvalid => ddr_aximm_ma_wvalid_o, -- out std_logic;
m00_axi_wready => ddr_aximm_ma_wready_i, -- in std_logic;
m00_axi_bid => ddr_aximm_ma_bid_int, -- in std_logic_vector ( 3 downto 0 );
m00_axi_bid => ddr_aximm_ma_bid_i, -- in std_logic_vector ( 3 downto 0 );
m00_axi_bresp => ddr_aximm_ma_bresp_i, -- in std_logic_vector ( 1 downto 0 );
m00_axi_bvalid => ddr_aximm_ma_bvalid_i, -- in std_logic;
m00_axi_bready => ddr_aximm_ma_bready_o, -- out std_logic;
m00_axi_arid => ddr_aximm_ma_arid_int, -- out std_logic_vector ( 3 downto 0 );
m00_axi_arid => ddr_aximm_ma_arid_o, -- out std_logic_vector ( 3 downto 0 );
m00_axi_araddr => ddr_aximm_ma_araddr_o, -- out std_logic_vector ( 31 downto 0 );
m00_axi_arlen => ddr_aximm_ma_arlen_o, -- out std_logic_vector ( 7 downto 0 );
m00_axi_arsize => ddr_aximm_ma_arsize_o, -- out std_logic_vector ( 2 downto 0 );
......@@ -781,7 +775,7 @@ begin
m00_axi_arqos => ddr_aximm_ma_arqos_o, -- out std_logic_vector ( 3 downto 0 );
m00_axi_arvalid => ddr_aximm_ma_arvalid_o, -- out std_logic;
m00_axi_arready => ddr_aximm_ma_arready_i, -- in std_logic;
m00_axi_rid => ddr_aximm_ma_rid_int, -- in std_logic_vector ( 3 downto 0 );
m00_axi_rid => ddr_aximm_ma_rid_i, -- in std_logic_vector ( 3 downto 0 );
m00_axi_rdata => ddr_aximm_ma_rdata_i, -- in std_logic_vector ( 255 downto 0 );
m00_axi_rresp => ddr_aximm_ma_rresp_i, -- in std_logic_vector ( 1 downto 0 );
m00_axi_rlast => ddr_aximm_ma_rlast_i, -- in std_logic;
......@@ -789,9 +783,4 @@ begin
m00_axi_rready => ddr_aximm_ma_rready_o -- out std_logic
);
ddr_aximm_ma_awid_o <= ddr_aximm_ma_awid_int(0 downto 0);
ddr_aximm_ma_bid_int <= "000" & ddr_aximm_ma_bid_i;
ddr_aximm_ma_arid_o <= ddr_aximm_ma_arid_int(0 downto 0);
ddr_aximm_ma_rid_int <= "000" & ddr_aximm_ma_rid_i;
end rtl;
hdl/modules/dbe_wishbone/wb_acq_core_mux/wb_acq_core_mux_plain.vhd
View file @ 675376c3
......@@ -121,7 +121,7 @@ port
-----------------------------
-- DDR3 SDRAM Interface
-----------------------------
ddr_aximm_ma_awid_o : out std_logic_vector (0 downto 0);
ddr_aximm_ma_awid_o : out std_logic_vector (3 downto 0);
ddr_aximm_ma_awaddr_o : out std_logic_vector (31 downto 0);
ddr_aximm_ma_awlen_o : out std_logic_vector (7 downto 0);
ddr_aximm_ma_awsize_o : out std_logic_vector (2 downto 0);
......@@ -138,10 +138,10 @@ port
ddr_aximm_ma_wvalid_o : out std_logic;
ddr_aximm_ma_wready_i : in std_logic;
ddr_aximm_ma_bready_o : out std_logic;
ddr_aximm_ma_bid_i : in std_logic_vector (0 downto 0);
ddr_aximm_ma_bid_i : in std_logic_vector (3 downto 0);
ddr_aximm_ma_bresp_i : in std_logic_vector (1 downto 0);
ddr_aximm_ma_bvalid_i : in std_logic;
ddr_aximm_ma_arid_o : out std_logic_vector (0 downto 0);
ddr_aximm_ma_arid_o : out std_logic_vector (3 downto 0);
ddr_aximm_ma_araddr_o : out std_logic_vector (31 downto 0);
ddr_aximm_ma_arlen_o : out std_logic_vector (7 downto 0);
ddr_aximm_ma_arsize_o : out std_logic_vector (2 downto 0);
......@@ -153,7 +153,7 @@ port
ddr_aximm_ma_arvalid_o : out std_logic;
ddr_aximm_ma_arready_i : in std_logic;
ddr_aximm_ma_rready_o : out std_logic;
ddr_aximm_ma_rid_i : in std_logic_vector (0 downto 0);
ddr_aximm_ma_rid_i : in std_logic_vector (3 downto 0);
ddr_aximm_ma_rdata_i : in std_logic_vector (g_ddr_payload_width-1 downto 0);
ddr_aximm_ma_rresp_i : in std_logic_vector (1 downto 0);
ddr_aximm_ma_rlast_i : in std_logic;
......
hdl/modules/dbe_wishbone/wb_pcie/bpm_axi_pkg.vhd
View file @ 675376c3
......@@ -7,7 +7,7 @@ library work;
package bpm_axi_pkg is
-- AXIMM constants
constant c_aximm_id_width : natural := 1;
constant c_aximm_id_width : natural := 4;
constant c_aximm_addr_width : natural := 32;
constant c_aximm_len_width : natural := 8;
constant c_aximm_size_width : natural := 3;
......
hdl/modules/dbe_wishbone/wb_pcie/wb_bpm_pcie.vhd
View file @ 675376c3
......@@ -66,7 +66,7 @@ port (
-- DDR memory controller interface --
ddr_aximm_sl_aclk_o : out std_logic;
ddr_aximm_sl_aresetn_o : out std_logic;
ddr_aximm_w_sl_awid_i : in std_logic_vector (0 downto 0);
ddr_aximm_w_sl_awid_i : in std_logic_vector (3 downto 0);
ddr_aximm_w_sl_awaddr_i : in std_logic_vector (31 downto 0);
ddr_aximm_w_sl_awlen_i : in std_logic_vector (7 downto 0);
ddr_aximm_w_sl_awsize_i : in std_logic_vector (2 downto 0);
......@@ -83,10 +83,10 @@ port (
ddr_aximm_w_sl_wvalid_i : in std_logic;
ddr_aximm_w_sl_wready_o : out std_logic;
ddr_aximm_w_sl_bready_i : in std_logic;
ddr_aximm_w_sl_bid_o : out std_logic_vector (0 downto 0);
ddr_aximm_w_sl_bid_o : out std_logic_vector (3 downto 0);
ddr_aximm_w_sl_bresp_o : out std_logic_vector (1 downto 0);
ddr_aximm_w_sl_bvalid_o : out std_logic;
ddr_aximm_r_sl_arid_i : in std_logic_vector (0 downto 0);
ddr_aximm_r_sl_arid_i : in std_logic_vector (3 downto 0);
ddr_aximm_r_sl_araddr_i : in std_logic_vector (31 downto 0);
ddr_aximm_r_sl_arlen_i : in std_logic_vector (7 downto 0);
ddr_aximm_r_sl_arsize_i : in std_logic_vector (2 downto 0);
......@@ -98,7 +98,7 @@ port (
ddr_aximm_r_sl_arvalid_i : in std_logic;
ddr_aximm_r_sl_arready_o : out std_logic;
ddr_aximm_r_sl_rready_i : in std_logic;
ddr_aximm_r_sl_rid_o : out std_logic_vector (0 downto 0 );
ddr_aximm_r_sl_rid_o : out std_logic_vector (3 downto 0 );
ddr_aximm_r_sl_rdata_o : out std_logic_vector (c_ddr_payload_width-1 downto 0);
ddr_aximm_r_sl_rresp_o : out std_logic_vector (1 downto 0 );
ddr_aximm_r_sl_rlast_o : out std_logic;
......@@ -181,7 +181,7 @@ architecture rtl of wb_bpm_pcie is
-- DDR memory controller interface --
ddr_axi_aclk_o : out std_logic;
ddr_axi_aresetn_o : out std_logic;
ddr_axi_awid : in STD_LOGIC_VECTOR ( 0 downto 0 );
ddr_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
ddr_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
ddr_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
ddr_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
......@@ -198,10 +198,10 @@ architecture rtl of wb_bpm_pcie is
ddr_axi_wvalid : in STD_LOGIC;
ddr_axi_wready : out STD_LOGIC;
ddr_axi_bready : in STD_LOGIC;
ddr_axi_bid : out STD_LOGIC_VECTOR ( 0 downto 0 );
ddr_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
ddr_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
ddr_axi_bvalid : out STD_LOGIC;
ddr_axi_arid : in STD_LOGIC_VECTOR ( 0 downto 0 );
ddr_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
ddr_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
ddr_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
ddr_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
......@@ -213,7 +213,7 @@ architecture rtl of wb_bpm_pcie is
ddr_axi_arvalid : in STD_LOGIC;
ddr_axi_arready : out STD_LOGIC;
ddr_axi_rready : in STD_LOGIC;
ddr_axi_rid : out STD_LOGIC_VECTOR ( 0 downto 0 );
ddr_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
ddr_axi_rdata : out STD_LOGIC_VECTOR ( c_ddr_payload_width-1 downto 0 );
ddr_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
ddr_axi_rlast : out STD_LOGIC;
......
hdl/modules/pcie/bpm_pcie.vhd
View file @ 675376c3
......@@ -69,7 +69,7 @@ entity bpm_pcie is
-- DDR memory controller interface --
ddr_axi_aclk_o : out std_logic;
ddr_axi_aresetn_o : out std_logic;
ddr_axi_awid : in STD_LOGIC_VECTOR ( 0 downto 0 );
ddr_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
ddr_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
ddr_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
ddr_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
......@@ -86,10 +86,10 @@ entity bpm_pcie is
ddr_axi_wvalid : in STD_LOGIC;
ddr_axi_wready : out STD_LOGIC;
ddr_axi_bready : in STD_LOGIC;
ddr_axi_bid : out STD_LOGIC_VECTOR ( 0 downto 0 );
ddr_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
ddr_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
ddr_axi_bvalid : out STD_LOGIC;
ddr_axi_arid : in STD_LOGIC_VECTOR ( 0 downto 0 );
ddr_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
ddr_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
ddr_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
ddr_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
......@@ -101,7 +101,7 @@ entity bpm_pcie is
ddr_axi_arvalid : in STD_LOGIC;
ddr_axi_arready : out STD_LOGIC;
ddr_axi_rready : in STD_LOGIC;
ddr_axi_rid : out STD_LOGIC_VECTOR ( 0 downto 0 );
ddr_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
ddr_axi_rdata : out STD_LOGIC_VECTOR ( c_ddr_payload_width-1 downto 0 );
ddr_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
ddr_axi_rlast : out STD_LOGIC;
......
hdl/modules/pcie/common/ddr_Transact.vhd
View file @ 675376c3
......@@ -79,7 +79,7 @@ entity DDR_Transact is
--AXI4 interface
s_axi_aclk_out : out std_logic;
s_axi_aresetn_out : out std_logic;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
......@@ -96,10 +96,10 @@ entity DDR_Transact is
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
......@@ -111,7 +111,7 @@ entity DDR_Transact is
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( c_ddr_payload_width-1 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
......@@ -133,7 +133,7 @@ architecture Behavioral of DDR_Transact is
-- ----------------------------------------------------------------------------
signal ddr_ui_clk, ddr_mmcm_locked : std_logic;
signal ddr_ui_rst, irconnect_arstn, ddr_axi_aresetn, pcie_axi_aresetn : std_logic;
signal ddr_axi_awid, ddr_axi_arid, ddr_axi_bid, ddr_axi_rid : std_logic_vector(3 downto 0);
signal ddr_axi_awid, ddr_axi_arid, ddr_axi_bid, ddr_axi_rid : std_logic_vector(7 downto 0);
signal pcie_axi_awaddr, ddr_axi_awaddr : std_logic_vector(31 downto 0);
signal pcie_axi_awlen, ddr_axi_awlen : std_logic_vector(7 downto 0);
signal pcie_axi_awsize, ddr_axi_awsize : std_logic_vector(2 downto 0);
......@@ -171,7 +171,7 @@ PORT MAP (
INTERCONNECT_ARESETN => irconnect_arstn,
S00_AXI_ARESET_OUT_N => pcie_axi_aresetn,
S00_AXI_ACLK => pcie_clk,
S00_AXI_AWID => "0",
S00_AXI_AWID => "0000",
S00_AXI_AWADDR => pcie_axi_awaddr,
S00_AXI_AWLEN => pcie_axi_awlen,
S00_AXI_AWSIZE => pcie_axi_awsize,
......@@ -191,7 +191,7 @@ PORT MAP (
S00_AXI_BRESP => pcie_axi_bresp,
S00_AXI_BVALID => pcie_axi_bvalid,
S00_AXI_BREADY => pcie_axi_bready,
S00_AXI_ARID => "0",
S00_AXI_ARID => "0000",
S00_AXI_ARADDR => pcie_axi_araddr,
S00_AXI_ARLEN => pcie_axi_arlen,
S00_AXI_ARSIZE => pcie_axi_arsize,
......
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