syn/afc_v3/*/dbe_bpm/*.xpr: set target language as Verilog (again)

syn/afc_v3//dbe_bpm/.xpr: set target language as Verilog (again)
680f4629 · Lucas Russo · bfa6f12d · 680f4629
Commit 680f4629 authored Dec 18, 2015 by Lucas Russo
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dbe_bpm.xpr hdl/syn/afc_v3/vivado/dbe_bpm/dbe_bpm.xpr +0 -1

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--- a/hdl/syn/afc_v3/vivado/dbe_bpm/dbe_bpm.xpr
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm/dbe_bpm.xpr
@@ -9,7 +9,6 @@
    <Option Name="Id" Val="96ca6d9a77034d48a4aba88faf50ee90"/>
    <Option Name="Part" Val="xc7a200tffg1156-1"/>
    <Option Name="CompiledLibDir" Val="$PPRDIR/../../../../../../../../../opt/Xilinx/Vivado/2015.2/data"/>
-    <Option Name="TargetLanguage" Val="VHDL"/>
    <Option Name="TargetSimulator" Val="ModelSim"/>
    <Option Name="BoardPart" Val=""/>
    <Option Name="SourceMgmtMode" Val="DisplayOnly"/>