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Commit 6913cfaa authored by Lucas Russo's avatar Lucas Russo
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fmc_active_clk: move module to dbe_wishbone/ directory

parent 82b8872c
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hdl/modules/dbe_wishbone/Manifest.py
View file @ 6913cfaa
......@@ -13,5 +13,6 @@ modules = { "local" : [
"wb_acq_core",
"wb_acq_core_mux",
"wb_pcie",
"wb_fmc_adc_common"
"wb_fmc_adc_common",
"wb_fmc_active_clk"
] };
hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd
View file @ 6913cfaa
......@@ -2155,6 +2155,129 @@ package dbe_wishbone_pkg is
);
end component;
component wb_fmc_active_clk
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_with_extra_wb_reg : boolean := false
);
port
(
sys_clk_i : in std_logic;
sys_rst_n_i : in std_logic;
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- External ports
-----------------------------
-- Si571 clock gen
si571_scl_pad_b : inout std_logic;
si571_sda_pad_b : inout std_logic;
fmc_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
spi_ad9510_cs_o : out std_logic;
spi_ad9510_sclk_o : out std_logic;
spi_ad9510_mosi_o : out std_logic;
spi_ad9510_miso_i : in std_logic := '0';
fmc_pll_function_o : out std_logic;
fmc_pll_status_i : in std_logic := '0';
-- AD9510 clock copy
fmc_fpga_clk_p_i : in std_logic := '0';
fmc_fpga_clk_n_i : in std_logic := '0';
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o : out std_logic;
-----------------------------
-- General ADC output signals and status
-----------------------------
-- General board status
fmc_pll_status_o : out std_logic;
-- fmc_fpga_clk_*_i bypass signals
fmc_fpga_clk_p_o : out std_logic;
fmc_fpga_clk_n_o : out std_logic
);
end component;
component xwb_fmc_active_clk
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_with_extra_wb_reg : boolean := false
);
port
(
sys_clk_i : in std_logic;
sys_rst_n_i : in std_logic;
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
-- Si571 clock gen
si571_scl_pad_b : inout std_logic;
si571_sda_pad_b : inout std_logic;
fmc_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
spi_ad9510_cs_o : out std_logic;
spi_ad9510_sclk_o : out std_logic;
spi_ad9510_mosi_o : out std_logic;
spi_ad9510_miso_i : in std_logic := '0';
fmc_pll_function_o : out std_logic;
fmc_pll_status_i : in std_logic := '0';
-- AD9510 clock copy
fmc_fpga_clk_p_i : in std_logic := '0';
fmc_fpga_clk_n_i : in std_logic := '0';
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o : out std_logic;
-----------------------------
-- General ADC output signals and status
-----------------------------
-- General board status
fmc_pll_status_o : out std_logic;
-- fmc_fpga_clk_*_i bypass signals
fmc_fpga_clk_p_o : out std_logic;
fmc_fpga_clk_n_o : out std_logic
);
end component;
--------------------------------------------------------------------
-- SDB Devices Structures
--------------------------------------------------------------------
......@@ -2311,4 +2434,22 @@ package dbe_wishbone_pkg is
version => x"00000001",
date => x"20160418",
name => "LNLS_ACOMMON_REGS ")));
-- FMC Active Clock
constant c_xwb_fmc_active_clk_regs_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity (0100)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"88c67d9c",
version => x"00000001",
date => x"20160418",
name => "LNLS_ACLK_REGS ")));
end dbe_wishbone_pkg;
hdl/modules/dbe_wishbone/wb_fmc_active_clk/Manifest.py 0 → 100644
View file @ 6913cfaa
files = [ "wb_fmc_active_clk.vhd",
"xwb_fmc_active_clk.vhd",
"wbgen/wb_fmc_active_clk_regs_pkg.vhd",
"wbgen/wb_fmc_active_clk_regs.vhd"
];
hdl/modules/dbe_wishbone/wb_fmc_active_clk/xwb_fmc_active_clk.vhd 0 → 100644
View file @ 6913cfaa
------------------------------------------------------------------------------
-- Title : Wishbone FMC Active Clock Interface
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2016-02-19
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top Module for the BPM with FMC250.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-19 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
entity xwb_fmc_active_clk is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_with_extra_wb_reg : boolean := false
);
port
(
sys_clk_i : in std_logic;
sys_rst_n_i : in std_logic;
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
-- Si571 clock gen
si571_scl_pad_b : inout std_logic;
si571_sda_pad_b : inout std_logic;
fmc_si571_oe_o : out std_logic;
-- AD9510 clock distribution PLL
spi_ad9510_cs_o : out std_logic;
spi_ad9510_sclk_o : out std_logic;
spi_ad9510_mosi_o : out std_logic;
spi_ad9510_miso_i : in std_logic := '0';
fmc_pll_function_o : out std_logic;
fmc_pll_status_i : in std_logic := '0';
-- AD9510 clock copy
fmc_fpga_clk_p_i : in std_logic := '0';
fmc_fpga_clk_n_i : in std_logic := '0';
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o : out std_logic;
-----------------------------
-- General ADC output signals and status
-----------------------------
-- General board status
fmc_pll_status_o : out std_logic;
-- fmc_fpga_clk_*_i bypass signals
fmc_fpga_clk_p_o : out std_logic;
fmc_fpga_clk_n_o : out std_logic
);
end xwb_fmc_active_clk;
architecture rtl of xwb_fmc_active_clk is
begin
cmp_wb_fmc_active_clk : wb_fmc_active_clk
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_with_extra_wb_reg => g_with_extra_wb_reg
)
port map (
sys_clk_i => sys_clk_i,
sys_rst_n_i => sys_rst_n_i,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_adr_i => wb_slv_i.adr,
wb_dat_i => wb_slv_i.dat,
wb_dat_o => wb_slv_o.dat,
wb_sel_i => wb_slv_i.sel,
wb_we_i => wb_slv_i.we,
wb_cyc_i => wb_slv_i.cyc,
wb_stb_i => wb_slv_i.stb,
wb_ack_o => wb_slv_o.ack,
wb_err_o => wb_slv_o.err,
wb_rty_o => wb_slv_o.rty,
wb_stall_o => wb_slv_o.stall,
-----------------------------
-- External ports
-----------------------------
-- Si571 clock gen
si571_scl_pad_b => si571_scl_pad_b,
si571_sda_pad_b => si571_sda_pad_b,
fmc_si571_oe_o => fmc_si571_oe_o,
-- AD9510 clock distribution PLL
spi_ad9510_cs_o => spi_ad9510_cs_o,
spi_ad9510_sclk_o => spi_ad9510_sclk_o,
spi_ad9510_mosi_o => spi_ad9510_mosi_o,
spi_ad9510_miso_i => spi_ad9510_miso_i,
fmc_pll_function_o => fmc_pll_function_o,
fmc_pll_status_i => fmc_pll_status_i,
-- AD9510 clock copy
fmc_fpga_clk_p_i => fmc_fpga_clk_p_i,
fmc_fpga_clk_n_i => fmc_fpga_clk_n_i,
-- Clock reference selection (TS3USB221)
fmc_clk_sel_o => fmc_clk_sel_o,
-----------------------------
-- General ADC output signals and status
-----------------------------
-- General board status -- General board status
fmc_pll_status_o => fmc_pll_status_o,
-- fmc_fpga_clk_*_i bypass signals
fmc_fpga_clk_p_o => fmc_fpga_clk_p_o,
fmc_fpga_clk_n_o => fmc_fpga_clk_n_o
);
end rtl;
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