wb_fmc516_test/verilog/*: initial verilog testbench (with errors)

69c2acd0 · Lucas Russo · 44d0a56d · 69c2acd0 · 69c2acd0 · 69c2acd0
Commit 69c2acd0 authored Nov 15, 2012 by Lucas Russo
9 changed files
--- a/hdl/testbench/wishbone/wb_fmc516_test/verilog/Makefile
+++ b/hdl/testbench/wishbone/wb_fmc516_test/verilog/Makefile
--- a/hdl/testbench/wishbone/wb_fmc516_test/verilog/Manifest.py
+++ b/hdl/testbench/wishbone/wb_fmc516_test/verilog/Manifest.py
+action = "simulation"
+target = "xilinx"
+
+modules = {"local" : "../../../.." }
+files = ["wb_fmc516_tb.v", "defines.v", "timescale.v",
+			"clk_rst.v"]
+
+vlog_opt = "-i ../../../../sim/regs -i ../../../../sim"
--- a/hdl/testbench/wishbone/wb_fmc516_test/verilog/clk_rst.v
+++ b/hdl/testbench/wishbone/wb_fmc516_test/verilog/clk_rst.v
+`include "timescale.v"
+`include "defines.v"
+
+module clk_rst(
+  clk_sys_o,
+  clk_adc_o,
+  clk_100mhz_o,
+  clk_200mhz_o,
+  rstn_o
+);
+
+  // Defaults parameters
+  parameter CLK_SYS_PERIOD = `CLK_SYS_PERIOD;
+  parameter CLK_ADC_PERIOD = `CLK_ADC_PERIOD;
+
+  localparam CLK_100MHZ_PERIOD = `CLK_100MHZ_PERIOD;
+  localparam CLK_200MHZ_PERIOD = `CLK_200MHZ_PERIOD;
+
+  // Output Clocks
+  output reg
+    clk_sys_o,
+    clk_adc_o,
+    clk_100mhz_o,
+    clk_200mhz_o;
+
+  // Output Reset
+  output reg rstn_o;
+
+  // Reset generate
+  initial
+  begin
+    clk_sys_o = 0;
+    clk_adc_o = 0;
+    clk_100mhz_o = 0;
+    clk_200mhz_o = 0;
+    rstn_o = 0;
+    #(`RST_SYS_DELAY)
+    rstn_o = 1;
+  end
+
+  // Clock Generation
+  always #(CLK_SYS_PERIOD/2) clk_sys_o <= ~clk_sys_o;
+  always #(CLK_ADC_PERIOD/2) clk_adc_o <= ~clk_adc_o;
+  always #(CLK_100MHZ_PERIOD/2) clk_100mhz_o <= ~clk_100mhz_o;
+  always #(CLK_200MHZ_PERIOD/2) clk_200mhz_o <= ~clk_200mhz_o;
+
+endmodule
--- a/hdl/testbench/wishbone/wb_fmc516_test/verilog/defines.v
+++ b/hdl/testbench/wishbone/wb_fmc516_test/verilog/defines.v
+/*******************************
+ * Wishbone definitions
+ *******************************/
+
+// Wishbone Reference Clock
+`define WB_CLOCK_PERIOD 10.00
+`define WB_RESET_DELAY (4*`WB_CLOCK_PERIOD)
+// Wishbone Data Width
+`define WB_DATA_BUS_WIDTH 32
+// Wishbone Address Width
+`define WB_ADDRESS_BUS_WIDTH 32
+
+/*******************************
+ * ADC (FMC516) definitions
+ *******************************/
+ `define ADC_DATA_WIDTH 16
+
+/*******************************
+ * General definitions
+ *******************************/
+
+// 100 MHz clock
+`define CLK_SYS_PERIOD 10.00
+// 100 MHz clock
+`define CLK_100MHZ_PERIOD 10.00
+// 200 MHz clock
+`define CLK_200MHZ_PERIOD 5.00
+// 250 MHz clock
+`define CLK_ADC_PERIOD 4.0
+
+// Reset Delay
+`define RST_SYS_DELAY  (4*CLK_SYS_PERIOD)
--- a/hdl/testbench/wishbone/wb_fmc516_test/verilog/isim_cmd
+++ b/hdl/testbench/wishbone/wb_fmc516_test/verilog/isim_cmd
+run 5000 ns
--- a/hdl/testbench/wishbone/wb_fmc516_test/verilog/run.sh
+++ b/hdl/testbench/wishbone/wb_fmc516_test/verilog/run.sh
+#!/bin/bash
+
+# Tests for empty parameter
+if [ -z $1 ] ; then
+	echo "You must specify a top module testbench!";
+	exit 1;
+fi
+
+make && make fuse TOP_MODULE=$1 && ./isim_proj -view wave.wcfg -tclbatch isim_cmd -gui
--- a/hdl/testbench/wishbone/wb_fmc516_test/verilog/timescale.v
+++ b/hdl/testbench/wishbone/wb_fmc516_test/verilog/timescale.v
+// reference time = 1ns 
+// precision time = 1ps
+`timescale 1ns/1ps
--- a/hdl/testbench/wishbone/wb_fmc516_test/verilog/wave.wcfg
+++ b/hdl/testbench/wishbone/wb_fmc516_test/verilog/wave.wcfg
--- a/hdl/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v
+++ b/hdl/testbench/wishbone/wb_fmc516_test/verilog/wb_fmc516_tb.v