"wb_fmc516/wb_fmc516.vhd: small cleanup and update xwb_spi interface"

The xwb_spi interface was changed and will be referenced in the next commit (update submodule)

"wb_fmc516/wb_fmc516.vhd: small cleanup and update xwb_spi interface"
The xwb_spi interface was changed and will be referenced in the next commit (update submodule)
7191ed99 · Lucas Russo · 0f612e39 · 7191ed99
Commit 7191ed99 authored Mar 19, 2013 by Lucas Russo
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wb_fmc516.vhd hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd +3 -21

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--- a/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd
+++ b/hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd
@@ -411,8 +411,6 @@ architecture rtl of wb_fmc516 is
  -- System SPI signals
  -----------------------------
  signal sys_spi_din                        : std_logic;
-  -- delayed signal
-  signal sys_spi_din_d                      : std_logic_vector(3 downto 0);
  signal sys_spi_dout                       : std_logic;
  signal sys_spi_ss_int                     : std_logic_vector(7 downto 0);
  signal sys_spi_clk                        : std_logic;
@@ -1182,12 +1180,8 @@ begin
    pad_cs_o                                => sys_spi_ss_int,
    pad_sclk_o                              => sys_spi_clk,
    pad_mosi_o                              => sys_spi_dout,
-    --pad_miso_i                              => sys_spi_din_d(sys_spi_din_d'left),
    pad_miso_i                              => sys_spi_din,
-    --pad_mosi_o                              => open,
-    --pad_miso_i                              => '0',
-    --pad_miosio_b                            => sys_spi_data_b
-    oen_o                                   => sys_spi_miosio_oe_n
+    pad_oen_o                               => sys_spi_miosio_oe_n
  );

  -- Output SPI clock
@@ -1202,19 +1196,6 @@ begin
  sys_spi_cs_adc2_n_o <= sys_spi_ss_int(2);           -- SPI ADC CS channel 2
  sys_spi_cs_adc3_n_o <= sys_spi_ss_int(3);           -- SPI ADC CS channel 3

-  -- Add some FF after the input pin to solve timing problem.
-  --p_adc_spi : process (sys_clk_i)
-  --begin
-  --  if rising_edge(sys_clk_i) then
-  --    if sys_rst_sync_n = '0' then
-  --      sys_spi_din_d <= (others => '0');
-  --    else
-  --      sys_spi_din_d <= sys_spi_din_d(sys_spi_din_d'left-1 downto 0) &
-  --                          sys_spi_din;
-  --    end if;
-  --  end if;
-  --end process;
-
  -- Not used wishbone signals
  cbar_master_in(2).rty                     <= '0';

@@ -1243,7 +1224,8 @@ begin
    pad_cs_o                                => fmc_lmk_uwire_ss_int,
    pad_sclk_o                              => fmc_lmk_uwire_clk,
    pad_mosi_o                              => lmk_uwire_data_o,
-    pad_miso_i                              => '0'
+    pad_miso_i                              => '0',
+    pad_oen_o                               => open
  );
  --
  -- Output Microwire LMK clock