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Beam Positoning Monitor - Gateware
Commit 73782143 authored by Adrian Byszuk's avatar Adrian Byszuk
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Stall PCIe configuration handling during DMA

parent f79a3124
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Showing with 9 additions and 8 deletions
hdl/modules/pcie/bpm_pcie.vhd
View file @ 73782143
......@@ -128,7 +128,7 @@ architecture Behavioral of bpm_pcie is
signal DDR_Ready : std_logic;
signal ddr_reset : std_logic;
signal ddr_axi_reset : std_logic;
signal wbone_clk : std_logic;
signal wb_wr_we : std_logic;
signal wb_wr_wsof : std_logic;
......@@ -169,7 +169,6 @@ architecture Behavioral of bpm_pcie is
signal cfg_dcommand2 : std_logic_vector (16-1 downto 0);
signal tx_cfg_req : std_logic;
signal pl_initial_link_width : std_logic_vector (3-1 downto 0);
signal pl_lane_reversal_mode : std_logic_vector (2-1 downto 0);
signal pl_link_gen2_cap : std_logic;
......@@ -243,6 +242,7 @@ architecture Behavioral of bpm_pcie is
signal cfg_interrupt_assert : std_logic;
signal cfg_interrupt_msixenable : std_logic;
signal cfg_interrupt_msixfm : std_logic;
signal cfg_turnoff_ok : std_logic;
signal cfg_to_turnoff : std_logic;
signal cfg_pm_wake : std_logic;
......@@ -337,13 +337,13 @@ begin
cfg_err_cpl_timeout <= '0';
cfg_err_cpl_abort <= '0';
cfg_err_cpl_unexpect <= '0';
cfg_err_posted <= '1';
cfg_err_locked <= '1';
cfg_err_posted <= '0';
cfg_err_locked <= '0';
cfg_err_tlp_cpl_header <= (others => '0');
cfg_trn_pending <= '0';
cfg_pm_wake <= '0';
--
fc_sel <= (others => '0');
fc_sel <= "000";
pl_directed_link_auton <= '0';
pl_directed_link_change <= (others => '0');
......@@ -351,7 +351,6 @@ begin
pl_directed_link_width <= (others => '0');
pl_upstream_prefer_deemph <= '0';
tx_cfg_gnt <= '1';
s_axis_tx_tuser <= s_axis_tx_tdsc & '0' & s_axis_tx_terrfwd & '0';
m_axis_rx_terrfwd <= m_axis_rx_tuser(1);
m_axis_rx_tbar_hit <= m_axis_rx_tuser(8 downto 2);
......@@ -690,6 +689,7 @@ theTlpControl: entity work.tlpControl
s_axis_tx_tdsc => s_axis_tx_tdsc ,
tx_buf_av => tx_buf_av ,
s_axis_tx_terrfwd => s_axis_tx_terrfwd ,
tx_cfg_gnt => tx_cfg_gnt,
user_clk => user_clk ,
user_reset => user_reset ,
......@@ -829,8 +829,7 @@ DDRs_ctrl_module: entity work.DDR_Transact
pcie_clk => user_clk,
sys_reset => ddr_sys_rst
);
Wishbone_intf: entity work.wb_transact
port map(
-- PCIE user clk
......
hdl/modules/pcie/common/tlpControl.vhd
View file @ 73782143
......@@ -120,6 +120,7 @@ entity tlpControl is
s_axis_tx_tready : in std_logic;
s_axis_tx_tdsc : out std_logic;
tx_buf_av : in std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
tx_cfg_gnt : out std_logic;
-- Interrupt Interface
cfg_interrupt : out std_logic;
......@@ -275,6 +276,7 @@ begin
wb_FIFO_re <= wb_FIFO_RdEn_i;
wb_timeout <= Tx_wb_TimeOut;
tx_cfg_gnt <= not(DMA_us_Busy_i) or DMA_us_Tout;
-- Rx TLP interface
rx_Itf :
......
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