platform/virtex6/*: update chipscope .ngc files

77bb18c7 · Lucas Russo · b5817756 · 77bb18c7 · 77bb18c7 · 77bb18c7
Commit 77bb18c7 authored Dec 12, 2012 by Lucas Russo
4 changed files
--- a/hdl/platform/virtex6/chipscope/chipscope_ila.ngc
+++ b/hdl/platform/virtex6/chipscope/chipscope_ila.ngc
--- a/hdl/platform/virtex6/chipscope/chipscope_ila.vhd
+++ b/hdl/platform/virtex6/chipscope/chipscope_ila.vhd
@@ -8,7 +8,7 @@
 -- \   \   \/     Version    : 13.4
 --  \   \         Application: XILINX CORE Generator
 --  /   /         Filename   : chipscope_ila.vhd
-- /___/   /\     Timestamp  : Thu Oct 11 16:52:09 BRT 2012
+-- /___/   /\     Timestamp  : Wed Dec 12 15:31:40 BRST 2012
 -- \   \  /  \
 --  \___\/\___\
 --

--- a/hdl/platform/virtex6/chipscope/icon_1_port/chipscope_icon_1_port.ngc
+++ b/hdl/platform/virtex6/chipscope/icon_1_port/chipscope_icon_1_port.ngc
--- a/hdl/platform/virtex6/chipscope/icon_1_port/chipscope_icon_1_port.vhd
+++ b/hdl/platform/virtex6/chipscope/icon_1_port/chipscope_icon_1_port.vhd
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012 Xilinx, Inc.
+-- All Rights Reserved
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor     : Xilinx
+-- \   \   \/     Version    : 13.4
+--  \   \         Application: XILINX CORE Generator
+--  /   /         Filename   : chipscope_icon_1_port.vhd
+-- /___/   /\     Timestamp  : Wed Dec 12 14:30:28 BRST 2012
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Design Name: VHDL Synthesis Wrapper
+-------------------------------------------------------------------------------
+-- This wrapper is used to integrate with Project Navigator and PlanAhead
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY chipscope_icon_1_port IS
+  port (
+    CONTROL0: inout std_logic_vector(35 downto 0));
+END chipscope_icon_1_port;
+
+ARCHITECTURE chipscope_icon_1_port_a OF chipscope_icon_1_port IS
+BEGIN
+
+END chipscope_icon_1_port_a;