modules/*/wb_acq_core: rename ddr3_read to ddr3_ui_read

This is a more descriptive name, as the interface is specific to the Xilinx UI interface.

modules/*/wb_acq_core: rename ddr3_read to ddr3_ui_read
This is a more descriptive name, as the interface is specific to the Xilinx UI interface.
81176172 · Lucas Russo · 92014a4b · 81176172 · 81176172 · 81176172
Commit 81176172 authored Dec 07, 2015 by Lucas Russo
4 changed files
--- a/hdl/modules/dbe_wishbone/wb_acq_core/Manifest.py
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/Manifest.py
@@ -8,7 +8,7 @@ files = ["wb_acq_core.vhd",
        "acq_fwft_fifo.vhd",
        "fc_source.vhd",
        "acq_ddr3_ui_write.vhd",
-        "acq_ddr3_read.vhd",
+        "acq_ddr3_ui_read.vhd",
        "acq_cnt.vhd",
        "acq_sel_chan.vhd",
        "acq_2_diff_cnt.vhd",

--- a/hdl/modules/dbe_wishbone/wb_acq_core/acq_core_pkg.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/acq_core_pkg.vhd
@@ -690,7 +690,7 @@ package acq_core_pkg is
  );
  end component;

-  component acq_ddr3_read
+  component acq_ddr3_ui_read
  generic
  (
    g_acq_addr_width                          : natural := 32;

--- a/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_read.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_read.vhd
@@ -34,7 +34,7 @@ use work.acq_core_pkg.all;
 -- DBE common cores
 use work.dbe_common_pkg.all;

-entity acq_ddr3_read is
+entity acq_ddr3_ui_read is
 generic
 (
  g_acq_addr_width                          : natural := 32;
@@ -94,9 +94,9 @@ port
  ui_app_req_o                              : out std_logic;
  ui_app_gnt_i                              : in std_logic
 );
-end acq_ddr3_read;
+end acq_ddr3_ui_read;

-architecture rtl of acq_ddr3_read is
+architecture rtl of acq_ddr3_ui_read is

  alias c_acq_channels : t_acq_chan_param_array(g_acq_num_channels-1 downto 0) is g_acq_channels;

@@ -177,7 +177,7 @@ begin

  -- g_acq_addr_width != g_ddr_addr_width is not supported!
  assert (g_acq_addr_width = g_ddr_addr_width)
-  report "[acq_ddr3_read] Different address widths are not supported!"
+  report "[acq_ddr3_ui_read] Different address widths are not supported!"
  severity error;

  -----------------------------------------------------------------------------

--- a/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd
@@ -978,7 +978,7 @@ begin
    sim_in_rb <= ddr3_wr_all_trans_done_l;
    ddr3_rb_lmt_rb_rst <= not ddr3_wr_all_trans_done_l;

-    cmp_acq_ddr3_read : acq_ddr3_read
+    cmp_acq_ddr3_ui_read : acq_ddr3_ui_read
    generic map
    (
      g_acq_addr_width                      => g_acq_addr_width,