Skip to content

B
Beam Positoning Monitor - Gateware
Commit 820296c5 authored by Lucas Russo's avatar Lucas Russo
Browse files
Options

hdl/modules/dbe_wishbone/*: rename acq_core_2_to_1_mux to acq_core_mux 

Now, we can generate muxed acquisition cores from 2 to 8,
instead of just 2.
parent edc62ae5
Hide whitespace changes
Inline Side-by-side
Showing with 18 additions and 18 deletions
hdl/modules/dbe_wishbone/Manifest.py
View file @ 820296c5
......@@ -10,6 +10,6 @@ modules = { "local" : [
"wb_dbe_periph",
"wb_rs232_syscon",
"wb_acq_core",
"wb_acq_core_2_to_1_mux",
"wb_acq_core_mux",
"wb_pcie"
] };
hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd
View file @ 820296c5
......@@ -1320,7 +1320,7 @@ package dbe_wishbone_pkg is
);
end component;
component wb_acq_core_2_to_1_mux
component wb_acq_core_mux
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
......@@ -1444,7 +1444,7 @@ package dbe_wishbone_pkg is
);
end component;
component xwb_acq_core_2_to_1_mux
component xwb_acq_core_mux
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
......
hdl/modules/dbe_wishbone/wb_acq_core_2_to_1_mux/Manifest.py deleted 100644 → 0
View file @ edc62ae5
files = ["wb_acq_core_2_to_1_mux.vhd",
"wb_acq_core_2_to_1_mux_plain.vhd",
"xwb_acq_core_2_to_1_mux.vhd",
];
hdl/modules/dbe_wishbone/wb_acq_core_mux/Manifest.py 0 → 100644
View file @ 820296c5
files = ["wb_acq_core_mux.vhd",
"wb_acq_core_mux_plain.vhd",
"xwb_acq_core_mux.vhd",
];
hdl/modules/dbe_wishbone/wb_acq_core_2_to_1_mux/wb_acq_core_2_to_1_mux.vhd → hdl/modules/dbe_wishbone/wb_acq_core_mux/wb_acq_core_mux.vhd
View file @ 820296c5
......@@ -41,7 +41,7 @@ use work.bpm_axi_pkg.all;
-- Platform ipcores
use work.ipcores_pkg.all;
entity wb_acq_core_2_to_1_mux is
entity wb_acq_core_mux is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
......@@ -163,9 +163,9 @@ port
ddr_aximm_ma_rlast_i : in std_logic;
ddr_aximm_ma_rvalid_i : in std_logic
);
end wb_acq_core_2_to_1_mux;
end wb_acq_core_mux;
architecture rtl of wb_acq_core_2_to_1_mux is
architecture rtl of wb_acq_core_mux is
constant c_num_max_acq_cores : natural := 8;
......
hdl/modules/dbe_wishbone/wb_acq_core_2_to_1_mux/wb_acq_core_2_to_1_mux_plain.vhd → hdl/modules/dbe_wishbone/wb_acq_core_mux/wb_acq_core_mux_plain.vhd
View file @ 820296c5
......@@ -32,7 +32,7 @@ use work.acq_core_pkg.all;
-- DBE wishbone cores
use work.dbe_wishbone_pkg.all;
entity wb_acq_core_2_to_1_mux_plain is
entity wb_acq_core_mux_plain is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
......@@ -172,9 +172,9 @@ port
dbg_ddr_rb1_addr_o : out std_logic_vector(g_acq_addr_width-1 downto 0);
dbg_ddr_rb1_valid_o : out std_logic
);
end wb_acq_core_2_to_1_mux_plain;
end wb_acq_core_mux_plain;
architecture rtl of wb_acq_core_2_to_1_mux_plain is
architecture rtl of wb_acq_core_mux_plain is
signal acq0_val_low_array : t_acq_val_half_array(g_acq_num_channels-1 downto 0);
signal acq0_val_high_array : t_acq_val_half_array(g_acq_num_channels-1 downto 0);
......@@ -188,7 +188,7 @@ architecture rtl of wb_acq_core_2_to_1_mux_plain is
begin
cmp_wb_acq_core_2_to_1_mux : wb_acq_core_2_to_1_mux
cmp_wb_acq_core_mux : wb_acq_core_mux
generic map
(
g_interface_mode => g_interface_mode,
......
hdl/modules/dbe_wishbone/wb_acq_core_2_to_1_mux/xwb_acq_core_2_to_1_mux.vhd → hdl/modules/dbe_wishbone/wb_acq_core_mux/xwb_acq_core_mux.vhd
View file @ 820296c5
......@@ -38,7 +38,7 @@ use work.bpm_axi_pkg.all;
-- Platform ipcores
use work.ipcores_pkg.all;
entity xwb_acq_core_2_to_1_mux is
entity xwb_acq_core_mux is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
......@@ -116,9 +116,9 @@ port
ddr_aximm_w_ma_i : in t_aximm_w_master_in := cc_dummy_aximm_w_master_in;
ddr_aximm_w_ma_o : out t_aximm_w_master_out
);
end xwb_acq_core_2_to_1_mux;
end xwb_acq_core_mux;
architecture rtl of xwb_acq_core_2_to_1_mux is
architecture rtl of xwb_acq_core_mux is
signal acq_val_low_array : t_acq_val_half_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
signal acq_val_high_array : t_acq_val_half_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
......@@ -139,7 +139,7 @@ architecture rtl of xwb_acq_core_2_to_1_mux is
begin
cmp_wb_acq_core_2_to_1_mux : wb_acq_core_2_to_1_mux
cmp_wb_acq_core_mux : wb_acq_core_mux
generic map
(
g_interface_mode => g_interface_mode,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment