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Commit 824157fb authored by Lucas Russo's avatar Lucas Russo
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modules/*fmc*/*: fix xwb_i2c_master API change 

Recent general-cores update (commit c422896e)
changed the xwb_i2c_master API, turning the module
into a multi-master one. With this, simple modifications
had to be made in modules using it.
parent c422896e
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hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd
View file @ 824157fb
......@@ -428,22 +428,22 @@ architecture rtl of wb_fmc130m_4ch is
-----------------------------
-- EEPROM I2C Signals
-----------------------------
signal eeprom_i2c_scl_in : std_logic;
signal eeprom_i2c_scl_out : std_logic;
signal eeprom_i2c_scl_oe_n : std_logic;
signal eeprom_i2c_sda_in : std_logic;
signal eeprom_i2c_sda_out : std_logic;
signal eeprom_i2c_sda_oe_n : std_logic;
signal eeprom_i2c_scl_in : std_logic_vector(0 downto 0);
signal eeprom_i2c_scl_out : std_logic_vector(0 downto 0);
signal eeprom_i2c_scl_oe_n : std_logic_vector(0 downto 0);
signal eeprom_i2c_sda_in : std_logic_vector(0 downto 0);
signal eeprom_i2c_sda_out : std_logic_vector(0 downto 0);
signal eeprom_i2c_sda_oe_n : std_logic_vector(0 downto 0);
-----------------------------
-- LM75A I2C Signals
-----------------------------
signal lm75a_i2c_scl_in : std_logic;
signal lm75a_i2c_scl_out : std_logic;
signal lm75a_i2c_scl_oe_n : std_logic;
signal lm75a_i2c_sda_in : std_logic;
signal lm75a_i2c_sda_out : std_logic;
signal lm75a_i2c_sda_oe_n : std_logic;
signal lm75a_i2c_scl_in : std_logic_vector(0 downto 0);
signal lm75a_i2c_scl_out : std_logic_vector(0 downto 0);
signal lm75a_i2c_scl_oe_n : std_logic_vector(0 downto 0);
signal lm75a_i2c_sda_in : std_logic_vector(0 downto 0);
signal lm75a_i2c_sda_out : std_logic_vector(0 downto 0);
signal lm75a_i2c_sda_oe_n : std_logic_vector(0 downto 0);
-----------------------------
-- Trigger signals
......@@ -1255,11 +1255,11 @@ begin
sda_padoen_o => eeprom_i2c_sda_oe_n
);
eeprom_scl_pad_b <= eeprom_i2c_scl_out when eeprom_i2c_scl_oe_n = '0' else 'Z';
eeprom_i2c_scl_in <= eeprom_scl_pad_b;
eeprom_scl_pad_b <= eeprom_i2c_scl_out(0) when eeprom_i2c_scl_oe_n(0) = '0' else 'Z';
eeprom_i2c_scl_in(0) <= eeprom_scl_pad_b;
eeprom_sda_pad_b <= eeprom_i2c_sda_out when eeprom_i2c_sda_oe_n = '0' else 'Z';
eeprom_i2c_sda_in <= eeprom_sda_pad_b;
eeprom_sda_pad_b <= eeprom_i2c_sda_out(0) when eeprom_i2c_sda_oe_n(0) = '0' else 'Z';
eeprom_i2c_sda_in(0) <= eeprom_sda_pad_b;
-- Not used wishbone signals
--cbar_master_in(3).err <= '0';
......@@ -1291,11 +1291,11 @@ begin
sda_padoen_o => lm75a_i2c_sda_oe_n
);
lm75_scl_pad_b <= lm75a_i2c_scl_out when lm75a_i2c_scl_oe_n = '0' else 'Z';
lm75a_i2c_scl_in <= lm75_scl_pad_b;
lm75_scl_pad_b <= lm75a_i2c_scl_out(0) when lm75a_i2c_scl_oe_n(0) = '0' else 'Z';
lm75a_i2c_scl_in(0) <= lm75_scl_pad_b;
lm75_sda_pad_b <= lm75a_i2c_sda_out when lm75a_i2c_sda_oe_n = '0' else 'Z';
lm75a_i2c_sda_in <= lm75_sda_pad_b;
lm75_sda_pad_b <= lm75a_i2c_sda_out(0) when lm75a_i2c_sda_oe_n(0) = '0' else 'Z';
lm75a_i2c_sda_in(0) <= lm75_sda_pad_b;
-- Not used wishbone signals
--cbar_master_in(4).err <= '0';
......
hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wb_fmc250m_4ch.vhd
View file @ 824157fb
......@@ -453,12 +453,12 @@ architecture rtl of wb_fmc250m_4ch is
-----------------------------
-- EEPROM I2C Signals
-----------------------------
signal eeprom_i2c_scl_in : std_logic;
signal eeprom_i2c_scl_out : std_logic;
signal eeprom_i2c_scl_oe_n : std_logic;
signal eeprom_i2c_sda_in : std_logic;
signal eeprom_i2c_sda_out : std_logic;
signal eeprom_i2c_sda_oe_n : std_logic;
signal eeprom_i2c_scl_in : std_logic_vector(0 downto 0);
signal eeprom_i2c_scl_out : std_logic_vector(0 downto 0);
signal eeprom_i2c_scl_oe_n : std_logic_vector(0 downto 0);
signal eeprom_i2c_sda_in : std_logic_vector(0 downto 0);
signal eeprom_i2c_sda_out : std_logic_vector(0 downto 0);
signal eeprom_i2c_sda_oe_n : std_logic_vector(0 downto 0);
-----------------------------
-- Trigger signals
......@@ -1309,11 +1309,11 @@ begin
sda_padoen_o => eeprom_i2c_sda_oe_n
);
eeprom_scl_pad_b <= eeprom_i2c_scl_out when eeprom_i2c_scl_oe_n = '0' else 'Z';
eeprom_i2c_scl_in <= eeprom_scl_pad_b;
eeprom_scl_pad_b <= eeprom_i2c_scl_out(0) when eeprom_i2c_scl_oe_n(0) = '0' else 'Z';
eeprom_i2c_scl_in(0) <= eeprom_scl_pad_b;
eeprom_sda_pad_b <= eeprom_i2c_sda_out when eeprom_i2c_sda_oe_n = '0' else 'Z';
eeprom_i2c_sda_in <= eeprom_sda_pad_b;
eeprom_sda_pad_b <= eeprom_i2c_sda_out(0) when eeprom_i2c_sda_oe_n(0) = '0' else 'Z';
eeprom_i2c_sda_in(0) <= eeprom_sda_pad_b;
-- Not used wishbone signals
--cbar_master_in(3).err <= '0';
......
hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd
View file @ 824157fb
......@@ -413,12 +413,12 @@ architecture rtl of wb_fmc516 is
-----------------------------
-- System I2C signals
-----------------------------
signal sys_i2c_scl_in : std_logic;
signal sys_i2c_scl_out : std_logic;
signal sys_i2c_scl_oe_n : std_logic;
signal sys_i2c_sda_in : std_logic;
signal sys_i2c_sda_out : std_logic;
signal sys_i2c_sda_oe_n : std_logic;
signal sys_i2c_scl_in : std_logic_vector(0 downto 0);
signal sys_i2c_scl_out : std_logic_vector(0 downto 0);
signal sys_i2c_scl_oe_n : std_logic_vector(0 downto 0);
signal sys_i2c_sda_in : std_logic_vector(0 downto 0);
signal sys_i2c_sda_out : std_logic_vector(0 downto 0);
signal sys_i2c_sda_oe_n : std_logic_vector(0 downto 0);
-----------------------------
-- System SPI signals
......@@ -438,12 +438,12 @@ architecture rtl of wb_fmc516 is
-----------------------------
-- VCXO I2C signals
-----------------------------
signal vcxo_i2c_scl_in : std_logic;
signal vcxo_i2c_scl_out : std_logic;
signal vcxo_i2c_scl_oe_n : std_logic;
signal vcxo_i2c_sda_in : std_logic;
signal vcxo_i2c_sda_out : std_logic;
signal vcxo_i2c_sda_oe_n : std_logic;
signal vcxo_i2c_scl_in : std_logic_vector(0 downto 0);
signal vcxo_i2c_scl_out : std_logic_vector(0 downto 0);
signal vcxo_i2c_scl_oe_n : std_logic_vector(0 downto 0);
signal vcxo_i2c_sda_in : std_logic_vector(0 downto 0);
signal vcxo_i2c_sda_out : std_logic_vector(0 downto 0);
signal vcxo_i2c_sda_oe_n : std_logic_vector(0 downto 0);
-----------------------------
-- One Wire DS2431 (VMETRO Data) signals
......@@ -1173,11 +1173,11 @@ begin
);
-- Tri-state buffer for SDA and SCL
sys_i2c_scl_b <= sys_i2c_scl_out when sys_i2c_scl_oe_n = '0' else 'Z';
sys_i2c_scl_in <= sys_i2c_scl_b;
sys_i2c_scl_b <= sys_i2c_scl_out(0) when sys_i2c_scl_oe_n(0) = '0' else 'Z';
sys_i2c_scl_in(0) <= sys_i2c_scl_b;
sys_i2c_sda_b <= sys_i2c_sda_out when sys_i2c_sda_oe_n = '0' else 'Z';
sys_i2c_sda_in <= sys_i2c_sda_b;
sys_i2c_sda_b <= sys_i2c_sda_out(0) when sys_i2c_sda_oe_n(0) = '0' else 'Z';
sys_i2c_sda_in(0) <= sys_i2c_sda_b;
-- Not used wishbone signals
cbar_master_in(1).err <= '0';
......@@ -1295,12 +1295,12 @@ begin
sda_padoen_o => vcxo_i2c_sda_oe_n
);
vcxo_i2c_scl_b <= vcxo_i2c_scl_out when vcxo_i2c_scl_oe_n = '0' else 'Z';
vcxo_i2c_scl_in <= vcxo_i2c_scl_b;
vcxo_i2c_scl_b <= vcxo_i2c_scl_out(0) when vcxo_i2c_scl_oe_n(0) = '0' else 'Z';
vcxo_i2c_scl_in(0) <= vcxo_i2c_scl_b;
--vcxo_i2c_scl_o <= sys_i2c_scl_out when vcxo_i2c_scl_oe_n = '0' else 'Z';
vcxo_i2c_sda_b <= vcxo_i2c_sda_out when vcxo_i2c_sda_oe_n = '0' else 'Z';
vcxo_i2c_sda_in <= vcxo_i2c_sda_b;
vcxo_i2c_sda_b <= vcxo_i2c_sda_out(0) when vcxo_i2c_sda_oe_n(0) = '0' else 'Z';
vcxo_i2c_sda_in(0) <= vcxo_i2c_sda_b;
-- VCXO output enable. Controllable from the Wishbone Register Interface
vcxo_pd_l_o <= regs_out.fmc_ctl_vcxo_out_en_o;
......
hdl/modules/dbe_wishbone/wb_fmc_active_clk/wb_fmc_active_clk.vhd
View file @ 824157fb
......@@ -163,12 +163,12 @@ architecture rtl of wb_fmc_active_clk is
-----------------------------
-- VCXO Si571 I2C Signals
-----------------------------
signal si571_i2c_scl_in : std_logic;
signal si571_i2c_scl_out : std_logic;
signal si571_i2c_scl_oe_n : std_logic;
signal si571_i2c_sda_in : std_logic;
signal si571_i2c_sda_out : std_logic;
signal si571_i2c_sda_oe_n : std_logic;
signal si571_i2c_scl_in : std_logic_vector(0 downto 0);
signal si571_i2c_scl_out : std_logic_vector(0 downto 0);
signal si571_i2c_scl_oe_n : std_logic_vector(0 downto 0);
signal si571_i2c_sda_in : std_logic_vector(0 downto 0);
signal si571_i2c_sda_out : std_logic_vector(0 downto 0);
signal si571_i2c_sda_oe_n : std_logic_vector(0 downto 0);
-----------------------------
-- Components
......@@ -387,11 +387,11 @@ begin
sda_padoen_o => si571_i2c_sda_oe_n
);
si571_scl_pad_b <= si571_i2c_scl_out when si571_i2c_scl_oe_n = '0' else 'Z';
si571_i2c_scl_in <= si571_scl_pad_b;
si571_scl_pad_b <= si571_i2c_scl_out(0) when si571_i2c_scl_oe_n(0) = '0' else 'Z';
si571_i2c_scl_in(0) <= si571_scl_pad_b;
si571_sda_pad_b <= si571_i2c_sda_out when si571_i2c_sda_oe_n = '0' else 'Z';
si571_i2c_sda_in <= si571_sda_pad_b;
si571_sda_pad_b <= si571_i2c_sda_out(0) when si571_i2c_sda_oe_n(0) = '0' else 'Z';
si571_i2c_sda_in(0) <= si571_sda_pad_b;
-- Not used wishbone signals
--cbar_master_in(1).err <= '0';
......
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