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Commit 86d1a93b authored by Lucas Russo's avatar Lucas Russo
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wb_fmc130m_4ch: standardize FMC Monitor register 

First setp into making this register match
the one present at FMC250M board
parent 5783dffc
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Showing with 52 additions and 52 deletions
hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd
View file @ 86d1a93b
......@@ -711,13 +711,13 @@ begin
regs_in.adc_reserved_i <= (others => '0');
regs_in.clk_distrib_pll_status_i <= fmc_pll_status_i;
regs_in.clk_distrib_reserved_i <= (others => '0');
regs_in.monitor_temp_alarm_i <= fmc_lm75_temp_alarm_i;
regs_in.monitor_reserved_i <= (others => '0');
regs_in.fpga_ctrl_fmc_idelay0_rdy_i <= adc_idelay_rdy;
regs_in.fpga_ctrl_fmc_idelay1_rdy_i <= adc_idelay_rdy;
regs_in.fpga_ctrl_fmc_idelay2_rdy_i <= adc_idelay_rdy;
regs_in.fpga_ctrl_fmc_idelay3_rdy_i <= adc_idelay_rdy;
regs_in.fpga_ctrl_reserved1_i <= (others => '0');
regs_in.fpga_ctrl_temp_alarm_i <= fmc_lm75_temp_alarm_i;
regs_in.fpga_ctrl_reserved2_i <= (others => '0');
regs_in.idelay0_cal_val_i <= adc_fn_dly_out(0).data_chain.idelay.val;
regs_in.idelay0_cal_reserved_i <= (others => '0');
......@@ -1069,10 +1069,10 @@ begin
fs_clk(i) <= adc_out(i).adc_clk;
fs_clk2x(i) <= adc_out(i).adc_clk2x;
adc_data(c_num_adc_bits*(i+1)-1 downto c_num_adc_bits*i) <=
adc_out(i).adc_data when regs_out.fpga_ctrl_test_data_en_o = '0'
adc_out(i).adc_data when regs_out.monitor_test_data_en_o = '0'
else std_logic_vector(wbs_test_data(i));
adc_valid(i) <=
adc_out(i).adc_data_valid when regs_out.fpga_ctrl_test_data_en_o = '0'
adc_out(i).adc_data_valid when regs_out.monitor_test_data_en_o = '0'
else '1';
end generate;
......@@ -1286,9 +1286,9 @@ begin
end if;
end process;
wbs_dat(i) <= adc_out(i).adc_data when regs_out.fpga_ctrl_test_data_en_o = '0'
wbs_dat(i) <= adc_out(i).adc_data when regs_out.monitor_test_data_en_o = '0'
else std_logic_vector(wbs_test_data(i));
wbs_valid(i) <= adc_out(i).adc_data_valid when regs_out.fpga_ctrl_test_data_en_o = '0'
wbs_valid(i) <= adc_out(i).adc_data_valid when regs_out.monitor_test_data_en_o = '0'
else '1';
end generate;
end generate;
......
hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/doc/fmc130m_4ch_regs_wb.html
View file @ 86d1a93b
......@@ -559,10 +559,10 @@ wb_fmc_130m_4ch_csr_trigger_reserved_i[28:0]
</td>
<td class="td_pblock_right">
wb_fmc_130m_4ch_csr_monitor_temp_alarm_i
wb_fmc_130m_4ch_csr_monitor_test_data_en_o
</td>
<td class="td_arrow_right">
&larr;
&rarr;
</td>
</tr>
<tr>
......@@ -1035,10 +1035,10 @@ wb_fmc_130m_4ch_csr_fpga_ctrl_reserved1_i[1:0]
</td>
<td class="td_pblock_right">
wb_fmc_130m_4ch_csr_fpga_ctrl_test_data_en_o
wb_fmc_130m_4ch_csr_fpga_ctrl_temp_alarm_i
</td>
<td class="td_arrow_right">
&rarr;
&larr;
</td>
</tr>
<tr>
......@@ -2724,7 +2724,7 @@ LED2
LED1
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TEMP_ALARM
TEST_DATA_EN
</td>
<td >
......@@ -2739,9 +2739,9 @@ TEMP_ALARM
</table>
<ul>
<li><b>
TEMP_ALARM
</b>[<i>read-only</i>]: Temperate Alarm
<br>Temperature alarm from LM75 chips
TEST_DATA_EN
</b>[<i>read/write</i>]: Enable test data
<br>Write the address counter value instead of ADC data to Wishbone Streaming Interface
<li><b>
LED1
</b>[<i>read/write</i>]: Led 1
......@@ -3483,7 +3483,7 @@ RESERVED2[14:7]
RESERVED2[6:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TEST_DATA_EN
TEMP_ALARM
</td>
<td >
......@@ -3589,9 +3589,9 @@ RESERVED1
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's.
<li><b>
TEST_DATA_EN
</b>[<i>read/write</i>]: Enable test data
<br>Write the address counter value instead of ADC data to Wishbone Streaming Interface
TEMP_ALARM
</b>[<i>read-only</i>]: Temperature Alarm
<br>Temperature alarm from LM75 chips
<li><b>
RESERVED2
</b>[<i>read-only</i>]: Reserved
......
hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc130m_4ch_regs.h
View file @ 86d1a93b
......@@ -3,7 +3,7 @@
* File : fmc130m_4ch_regs.h
* Author : auto-generated by wbgen2 from fmc_130m_4ch_regs.wb
* Created : Mon Apr 18 08:40:44 2016
* Created : Mon Apr 18 08:48:17 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_130m_4ch_regs.wb
......@@ -67,8 +67,8 @@
/* definitions for register: Monitor and FMC status control register */
/* definitions for field: Temperate Alarm in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_TEMP_ALARM WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Enable test data in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_TEST_DATA_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Led 1 in reg: Monitor and FMC status control register */
#define WB_FMC_130M_4CH_CSR_MONITOR_LED1 WBGEN2_GEN_MASK(1, 1)
......@@ -151,8 +151,8 @@
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED1_W(value) WBGEN2_GEN_WRITE(value, 6, 2)
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED1_R(reg) WBGEN2_GEN_READ(reg, 6, 2)
/* definitions for field: Enable test data in reg: FPGA control */
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_TEST_DATA_EN WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Temperature Alarm in reg: FPGA control */
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_TEMP_ALARM WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Reserved in reg: FPGA control */
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED2_MASK WBGEN2_GEN_MASK(9, 23)
......
hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd
View file @ 86d1a93b
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fmc_130m_4ch_regs.vhd
-- Author : auto-generated by wbgen2 from fmc_130m_4ch_regs.wb
-- Created : Mon Apr 18 08:40:44 2016
-- Created : Mon Apr 18 08:48:17 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_130m_4ch_regs.wb
......@@ -41,6 +41,7 @@ architecture syn of wb_fmc_130m_4ch_csr is
signal wb_fmc_130m_4ch_csr_trigger_dir_int : std_logic ;
signal wb_fmc_130m_4ch_csr_trigger_term_int : std_logic ;
signal wb_fmc_130m_4ch_csr_trigger_trig_val_int : std_logic ;
signal wb_fmc_130m_4ch_csr_monitor_test_data_en_int : std_logic ;
signal wb_fmc_130m_4ch_csr_monitor_led1_int : std_logic ;
signal wb_fmc_130m_4ch_csr_monitor_led2_int : std_logic ;
signal wb_fmc_130m_4ch_csr_monitor_led3_int : std_logic ;
......@@ -53,7 +54,6 @@ signal wb_fmc_130m_4ch_csr_adc_shdn_int : std_logic ;
signal wb_fmc_130m_4ch_csr_adc_pga_int : std_logic ;
signal wb_fmc_130m_4ch_csr_fpga_ctrl_fmc_idelay_rst_int : std_logic ;
signal wb_fmc_130m_4ch_csr_fpga_ctrl_fmc_fifo_rst_int : std_logic ;
signal wb_fmc_130m_4ch_csr_fpga_ctrl_test_data_en_int : std_logic ;
signal wb_fmc_130m_4ch_csr_idelay0_cal_update_dly0 : std_logic ;
signal wb_fmc_130m_4ch_csr_idelay0_cal_update_int : std_logic ;
signal wb_fmc_130m_4ch_csr_idelay0_cal_line_int : std_logic_vector(16 downto 0);
......@@ -127,6 +127,7 @@ begin
wb_fmc_130m_4ch_csr_trigger_dir_int <= '0';
wb_fmc_130m_4ch_csr_trigger_term_int <= '0';
wb_fmc_130m_4ch_csr_trigger_trig_val_int <= '0';
wb_fmc_130m_4ch_csr_monitor_test_data_en_int <= '0';
wb_fmc_130m_4ch_csr_monitor_led1_int <= '0';
wb_fmc_130m_4ch_csr_monitor_led2_int <= '0';
wb_fmc_130m_4ch_csr_monitor_led3_int <= '0';
......@@ -139,7 +140,6 @@ begin
wb_fmc_130m_4ch_csr_adc_pga_int <= '0';
wb_fmc_130m_4ch_csr_fpga_ctrl_fmc_idelay_rst_int <= '0';
wb_fmc_130m_4ch_csr_fpga_ctrl_fmc_fifo_rst_int <= '0';
wb_fmc_130m_4ch_csr_fpga_ctrl_test_data_en_int <= '0';
wb_fmc_130m_4ch_csr_idelay0_cal_update_int <= '0';
wb_fmc_130m_4ch_csr_idelay0_cal_line_int <= "00000000000000000";
regs_o.idelay0_cal_val_load_o <= '0';
......@@ -239,11 +239,12 @@ begin
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
wb_fmc_130m_4ch_csr_monitor_test_data_en_int <= wrdata_reg(0);
wb_fmc_130m_4ch_csr_monitor_led1_int <= wrdata_reg(1);
wb_fmc_130m_4ch_csr_monitor_led2_int <= wrdata_reg(2);
wb_fmc_130m_4ch_csr_monitor_led3_int <= wrdata_reg(3);
end if;
rddata_reg(0) <= regs_i.monitor_temp_alarm_i;
rddata_reg(0) <= wb_fmc_130m_4ch_csr_monitor_test_data_en_int;
rddata_reg(1) <= wb_fmc_130m_4ch_csr_monitor_led1_int;
rddata_reg(2) <= wb_fmc_130m_4ch_csr_monitor_led2_int;
rddata_reg(3) <= wb_fmc_130m_4ch_csr_monitor_led3_int;
......@@ -281,7 +282,6 @@ begin
if (wb_we_i = '1') then
wb_fmc_130m_4ch_csr_fpga_ctrl_fmc_idelay_rst_int <= wrdata_reg(0);
wb_fmc_130m_4ch_csr_fpga_ctrl_fmc_fifo_rst_int <= wrdata_reg(1);
wb_fmc_130m_4ch_csr_fpga_ctrl_test_data_en_int <= wrdata_reg(8);
end if;
rddata_reg(0) <= wb_fmc_130m_4ch_csr_fpga_ctrl_fmc_idelay_rst_int;
rddata_reg(1) <= wb_fmc_130m_4ch_csr_fpga_ctrl_fmc_fifo_rst_int;
......@@ -290,7 +290,7 @@ begin
rddata_reg(4) <= regs_i.fpga_ctrl_fmc_idelay2_rdy_i;
rddata_reg(5) <= regs_i.fpga_ctrl_fmc_idelay3_rdy_i;
rddata_reg(7 downto 6) <= regs_i.fpga_ctrl_reserved1_i;
rddata_reg(8) <= wb_fmc_130m_4ch_csr_fpga_ctrl_test_data_en_int;
rddata_reg(8) <= regs_i.fpga_ctrl_temp_alarm_i;
rddata_reg(31 downto 9) <= regs_i.fpga_ctrl_reserved2_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
......@@ -420,7 +420,8 @@ begin
-- Trigger Value
regs_o.trigger_trig_val_o <= wb_fmc_130m_4ch_csr_trigger_trig_val_int;
-- Reserved
-- Temperate Alarm
-- Enable test data
regs_o.monitor_test_data_en_o <= wb_fmc_130m_4ch_csr_monitor_test_data_en_int;
-- Led 1
regs_o.monitor_led1_o <= wb_fmc_130m_4ch_csr_monitor_led1_int;
-- Led 2
......@@ -454,8 +455,7 @@ begin
-- FMC_IDELAY2_RDY
-- FMC_IDELAY3_RDY
-- Reserved
-- Enable test data
regs_o.fpga_ctrl_test_data_en_o <= wb_fmc_130m_4ch_csr_fpga_ctrl_test_data_en_int;
-- Temperature Alarm
-- Reserved
-- UPDATE
process (clk_sys_i, rst_n_i)
......
hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.wb
View file @ 86d1a93b
......@@ -103,13 +103,13 @@ peripheral {
prefix = "monitor";
field {
name = "Temperate Alarm";
prefix = "temp_alarm";
description = "Temperature alarm from LM75 chips";
name = "Enable test data";
description = "Write the address counter value instead of ADC data to Wishbone Streaming Interface";
prefix = "test_data_en";
type = BIT;
--size = 1;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
......@@ -343,13 +343,13 @@ peripheral {
};
field {
name = "Enable test data";
description = "Write the address counter value instead of ADC data to Wishbone Streaming Interface";
prefix = "test_data_en";
name = "Temperature Alarm";
prefix = "temp_alarm";
description = "Temperature alarm from LM75 chips";
type = BIT;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
--size = 1;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
......
hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs_pkg.vhd
View file @ 86d1a93b
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fmc_130m_4ch_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from fmc_130m_4ch_regs.wb
-- Created : Mon Apr 18 08:40:44 2016
-- Created : Mon Apr 18 08:48:17 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_130m_4ch_regs.wb
......@@ -25,7 +25,6 @@ package wb_fmc_130m_4ch_csr_wbgen2_pkg is
fmc_status_prst_i : std_logic;
fmc_status_reserved_i : std_logic_vector(27 downto 0);
trigger_reserved_i : std_logic_vector(28 downto 0);
monitor_temp_alarm_i : std_logic;
monitor_reserved_i : std_logic_vector(27 downto 0);
clk_distrib_pll_status_i : std_logic;
clk_distrib_reserved_i : std_logic_vector(27 downto 0);
......@@ -35,6 +34,7 @@ package wb_fmc_130m_4ch_csr_wbgen2_pkg is
fpga_ctrl_fmc_idelay2_rdy_i : std_logic;
fpga_ctrl_fmc_idelay3_rdy_i : std_logic;
fpga_ctrl_reserved1_i : std_logic_vector(1 downto 0);
fpga_ctrl_temp_alarm_i : std_logic;
fpga_ctrl_reserved2_i : std_logic_vector(22 downto 0);
idelay0_cal_val_i : std_logic_vector(4 downto 0);
idelay0_cal_reserved_i : std_logic_vector(8 downto 0);
......@@ -59,7 +59,6 @@ package wb_fmc_130m_4ch_csr_wbgen2_pkg is
fmc_status_prst_i => '0',
fmc_status_reserved_i => (others => '0'),
trigger_reserved_i => (others => '0'),
monitor_temp_alarm_i => '0',
monitor_reserved_i => (others => '0'),
clk_distrib_pll_status_i => '0',
clk_distrib_reserved_i => (others => '0'),
......@@ -69,6 +68,7 @@ package wb_fmc_130m_4ch_csr_wbgen2_pkg is
fpga_ctrl_fmc_idelay2_rdy_i => '0',
fpga_ctrl_fmc_idelay3_rdy_i => '0',
fpga_ctrl_reserved1_i => (others => '0'),
fpga_ctrl_temp_alarm_i => '0',
fpga_ctrl_reserved2_i => (others => '0'),
idelay0_cal_val_i => (others => '0'),
idelay0_cal_reserved_i => (others => '0'),
......@@ -93,6 +93,7 @@ package wb_fmc_130m_4ch_csr_wbgen2_pkg is
trigger_dir_o : std_logic;
trigger_term_o : std_logic;
trigger_trig_val_o : std_logic;
monitor_test_data_en_o : std_logic;
monitor_led1_o : std_logic;
monitor_led2_o : std_logic;
monitor_led3_o : std_logic;
......@@ -105,7 +106,6 @@ package wb_fmc_130m_4ch_csr_wbgen2_pkg is
adc_pga_o : std_logic;
fpga_ctrl_fmc_idelay_rst_o : std_logic;
fpga_ctrl_fmc_fifo_rst_o : std_logic;
fpga_ctrl_test_data_en_o : std_logic;
idelay0_cal_update_o : std_logic;
idelay0_cal_line_o : std_logic_vector(16 downto 0);
idelay0_cal_val_o : std_logic_vector(4 downto 0);
......@@ -131,6 +131,7 @@ package wb_fmc_130m_4ch_csr_wbgen2_pkg is
trigger_dir_o => '0',
trigger_term_o => '0',
trigger_trig_val_o => '0',
monitor_test_data_en_o => '0',
monitor_led1_o => '0',
monitor_led2_o => '0',
monitor_led3_o => '0',
......@@ -143,7 +144,6 @@ package wb_fmc_130m_4ch_csr_wbgen2_pkg is
adc_pga_o => '0',
fpga_ctrl_fmc_idelay_rst_o => '0',
fpga_ctrl_fmc_fifo_rst_o => '0',
fpga_ctrl_test_data_en_o => '0',
idelay0_cal_update_o => '0',
idelay0_cal_line_o => (others => '0'),
idelay0_cal_val_o => (others => '0'),
......@@ -198,7 +198,6 @@ tmp.fmc_status_pwr_good_i := f_x_to_zero(left.fmc_status_pwr_good_i) or f_x_to_z
tmp.fmc_status_prst_i := f_x_to_zero(left.fmc_status_prst_i) or f_x_to_zero(right.fmc_status_prst_i);
tmp.fmc_status_reserved_i := f_x_to_zero(left.fmc_status_reserved_i) or f_x_to_zero(right.fmc_status_reserved_i);
tmp.trigger_reserved_i := f_x_to_zero(left.trigger_reserved_i) or f_x_to_zero(right.trigger_reserved_i);
tmp.monitor_temp_alarm_i := f_x_to_zero(left.monitor_temp_alarm_i) or f_x_to_zero(right.monitor_temp_alarm_i);
tmp.monitor_reserved_i := f_x_to_zero(left.monitor_reserved_i) or f_x_to_zero(right.monitor_reserved_i);
tmp.clk_distrib_pll_status_i := f_x_to_zero(left.clk_distrib_pll_status_i) or f_x_to_zero(right.clk_distrib_pll_status_i);
tmp.clk_distrib_reserved_i := f_x_to_zero(left.clk_distrib_reserved_i) or f_x_to_zero(right.clk_distrib_reserved_i);
......@@ -208,6 +207,7 @@ tmp.fpga_ctrl_fmc_idelay1_rdy_i := f_x_to_zero(left.fpga_ctrl_fmc_idelay1_rdy_i)
tmp.fpga_ctrl_fmc_idelay2_rdy_i := f_x_to_zero(left.fpga_ctrl_fmc_idelay2_rdy_i) or f_x_to_zero(right.fpga_ctrl_fmc_idelay2_rdy_i);
tmp.fpga_ctrl_fmc_idelay3_rdy_i := f_x_to_zero(left.fpga_ctrl_fmc_idelay3_rdy_i) or f_x_to_zero(right.fpga_ctrl_fmc_idelay3_rdy_i);
tmp.fpga_ctrl_reserved1_i := f_x_to_zero(left.fpga_ctrl_reserved1_i) or f_x_to_zero(right.fpga_ctrl_reserved1_i);
tmp.fpga_ctrl_temp_alarm_i := f_x_to_zero(left.fpga_ctrl_temp_alarm_i) or f_x_to_zero(right.fpga_ctrl_temp_alarm_i);
tmp.fpga_ctrl_reserved2_i := f_x_to_zero(left.fpga_ctrl_reserved2_i) or f_x_to_zero(right.fpga_ctrl_reserved2_i);
tmp.idelay0_cal_val_i := f_x_to_zero(left.idelay0_cal_val_i) or f_x_to_zero(right.idelay0_cal_val_i);
tmp.idelay0_cal_reserved_i := f_x_to_zero(left.idelay0_cal_reserved_i) or f_x_to_zero(right.idelay0_cal_reserved_i);
......
hdl/sim/regs/wb_fmc130m_4ch_regs.vh
View file @ 86d1a93b
......@@ -17,8 +17,8 @@
`define WB_FMC_130M_4CH_CSR_TRIGGER_RESERVED_OFFSET 3
`define WB_FMC_130M_4CH_CSR_TRIGGER_RESERVED 32'hfffffff8
`define ADDR_WB_FMC_130M_4CH_CSR_MONITOR 6'h8
`define WB_FMC_130M_4CH_CSR_MONITOR_TEMP_ALARM_OFFSET 0
`define WB_FMC_130M_4CH_CSR_MONITOR_TEMP_ALARM 32'h00000001
`define WB_FMC_130M_4CH_CSR_MONITOR_TEST_DATA_EN_OFFSET 0
`define WB_FMC_130M_4CH_CSR_MONITOR_TEST_DATA_EN 32'h00000001
`define WB_FMC_130M_4CH_CSR_MONITOR_LED1_OFFSET 1
`define WB_FMC_130M_4CH_CSR_MONITOR_LED1 32'h00000002
`define WB_FMC_130M_4CH_CSR_MONITOR_LED2_OFFSET 2
......@@ -64,8 +64,8 @@
`define WB_FMC_130M_4CH_CSR_FPGA_CTRL_FMC_IDELAY3_RDY 32'h00000020
`define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED1_OFFSET 6
`define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED1 32'h000000c0
`define WB_FMC_130M_4CH_CSR_FPGA_CTRL_TEST_DATA_EN_OFFSET 8
`define WB_FMC_130M_4CH_CSR_FPGA_CTRL_TEST_DATA_EN 32'h00000100
`define WB_FMC_130M_4CH_CSR_FPGA_CTRL_TEMP_ALARM_OFFSET 8
`define WB_FMC_130M_4CH_CSR_FPGA_CTRL_TEMP_ALARM 32'h00000100
`define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED2_OFFSET 9
`define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED2 32'hfffffe00
`define ADDR_WB_FMC_130M_4CH_CSR_IDELAY0_CAL 6'h18
......
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