testbench/*/wb_acq_core/*: reduce TEST #5 as it was taking too much simulation time

testbench//wb_acq_core/: reduce TEST #5 as it was taking too much simulation time
871cf7ce · Lucas Russo · 4c5ea477 · 871cf7ce
Commit 871cf7ce authored Jul 13, 2016 by Lucas Russo
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wb_acq_core_tb.v ...acq_core_test/verilog/artix7/full_tb_mux/wb_acq_core_tb.v +1 -1

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--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wb_acq_core_tb.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wb_acq_core_tb.v
@@ -1800,7 +1800,7 @@ module wb_acq_core_tb;
    test_id = 5;
    n_shots = 16'h0001;
-    pre_trig_samples = 32'h00001000;
+    pre_trig_samples = 32'h00000400;
    post_trig_samples = 32'h00000000;
    ddr3_start_addr = 32'h00000000; // all zeros for now
    ddr3_end_addr = 32'h00100000;