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Commit 8b3d9071 authored by Lucas Russo's avatar Lucas Russo
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wb_fmc250m_4ch/wbgen: add fine delay selection registers 

This will be used to select each ADC lines
will be updated with the current delay value.
This feature is already available on FMC130M_4CH.
parent d66e8a89
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Showing with 2098 additions and 446 deletions
hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wbgen/wb_fmc250m_4ch_regs.h
View file @ 8b3d9071
......@@ -3,7 +3,7 @@
* File : wb_fmc250m_4ch_regs.h
* Author : auto-generated by wbgen2 from wb_fmc250m_4ch_regs.wb
* Created : Mon Apr 18 15:12:15 2016
* Created : Thu Oct 6 16:55:33 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc250m_4ch_regs.wb
......@@ -150,6 +150,20 @@
#define WB_FMC_250M_4CH_CSR_CH0_FN_DLY_RESERVED_DATA_INCDEC_DLY_W(value) WBGEN2_GEN_WRITE(value, 26, 6)
#define WB_FMC_250M_4CH_CSR_CH0_FN_DLY_RESERVED_DATA_INCDEC_DLY_R(reg) WBGEN2_GEN_READ(reg, 26, 6)
/* definitions for register: Channel 0 fine delay selection */
/* definitions for field: LINE in reg: Channel 0 fine delay selection */
#define WB_FMC_250M_4CH_CSR_CH0_FN_SEL_LINE_MASK WBGEN2_GEN_MASK(0, 17)
#define WB_FMC_250M_4CH_CSR_CH0_FN_SEL_LINE_SHIFT 0
#define WB_FMC_250M_4CH_CSR_CH0_FN_SEL_LINE_W(value) WBGEN2_GEN_WRITE(value, 0, 17)
#define WB_FMC_250M_4CH_CSR_CH0_FN_SEL_LINE_R(reg) WBGEN2_GEN_READ(reg, 0, 17)
/* definitions for field: Reserved in reg: Channel 0 fine delay selection */
#define WB_FMC_250M_4CH_CSR_CH0_FN_SEL_RESERVED_MASK WBGEN2_GEN_MASK(17, 15)
#define WB_FMC_250M_4CH_CSR_CH0_FN_SEL_RESERVED_SHIFT 17
#define WB_FMC_250M_4CH_CSR_CH0_FN_SEL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 17, 15)
#define WB_FMC_250M_4CH_CSR_CH0_FN_SEL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 17, 15)
/* definitions for register: Channel 0 coarse delay register */
/* definitions for field: Falling edge data delay in reg: Channel 0 coarse delay register */
......@@ -240,6 +254,20 @@
#define WB_FMC_250M_4CH_CSR_CH1_FN_DLY_RESERVED_DATA_INCDEC_DLY_W(value) WBGEN2_GEN_WRITE(value, 26, 6)
#define WB_FMC_250M_4CH_CSR_CH1_FN_DLY_RESERVED_DATA_INCDEC_DLY_R(reg) WBGEN2_GEN_READ(reg, 26, 6)
/* definitions for register: Channel 1 fine delay selection */
/* definitions for field: LINE in reg: Channel 1 fine delay selection */
#define WB_FMC_250M_4CH_CSR_CH1_FN_SEL_LINE_MASK WBGEN2_GEN_MASK(0, 17)
#define WB_FMC_250M_4CH_CSR_CH1_FN_SEL_LINE_SHIFT 0
#define WB_FMC_250M_4CH_CSR_CH1_FN_SEL_LINE_W(value) WBGEN2_GEN_WRITE(value, 0, 17)
#define WB_FMC_250M_4CH_CSR_CH1_FN_SEL_LINE_R(reg) WBGEN2_GEN_READ(reg, 0, 17)
/* definitions for field: Reserved in reg: Channel 1 fine delay selection */
#define WB_FMC_250M_4CH_CSR_CH1_FN_SEL_RESERVED_MASK WBGEN2_GEN_MASK(17, 15)
#define WB_FMC_250M_4CH_CSR_CH1_FN_SEL_RESERVED_SHIFT 17
#define WB_FMC_250M_4CH_CSR_CH1_FN_SEL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 17, 15)
#define WB_FMC_250M_4CH_CSR_CH1_FN_SEL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 17, 15)
/* definitions for register: Channel 1 coarse delay register */
/* definitions for field: Falling edge data delay in reg: Channel 1 coarse delay register */
......@@ -330,6 +358,20 @@
#define WB_FMC_250M_4CH_CSR_CH2_FN_DLY_RESERVED_DATA_INCDEC_DLY_W(value) WBGEN2_GEN_WRITE(value, 26, 6)
#define WB_FMC_250M_4CH_CSR_CH2_FN_DLY_RESERVED_DATA_INCDEC_DLY_R(reg) WBGEN2_GEN_READ(reg, 26, 6)
/* definitions for register: Channel 2 fine delay selection */
/* definitions for field: LINE in reg: Channel 2 fine delay selection */
#define WB_FMC_250M_4CH_CSR_CH2_FN_SEL_LINE_MASK WBGEN2_GEN_MASK(0, 17)
#define WB_FMC_250M_4CH_CSR_CH2_FN_SEL_LINE_SHIFT 0
#define WB_FMC_250M_4CH_CSR_CH2_FN_SEL_LINE_W(value) WBGEN2_GEN_WRITE(value, 0, 17)
#define WB_FMC_250M_4CH_CSR_CH2_FN_SEL_LINE_R(reg) WBGEN2_GEN_READ(reg, 0, 17)
/* definitions for field: Reserved in reg: Channel 2 fine delay selection */
#define WB_FMC_250M_4CH_CSR_CH2_FN_SEL_RESERVED_MASK WBGEN2_GEN_MASK(17, 15)
#define WB_FMC_250M_4CH_CSR_CH2_FN_SEL_RESERVED_SHIFT 17
#define WB_FMC_250M_4CH_CSR_CH2_FN_SEL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 17, 15)
#define WB_FMC_250M_4CH_CSR_CH2_FN_SEL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 17, 15)
/* definitions for register: Channel 2 coarse delay register */
/* definitions for field: Falling edge data delay in reg: Channel 2 coarse delay register */
......@@ -420,6 +462,20 @@
#define WB_FMC_250M_4CH_CSR_CH3_FN_DLY_RESERVED_DATA_INCDEC_DLY_W(value) WBGEN2_GEN_WRITE(value, 26, 6)
#define WB_FMC_250M_4CH_CSR_CH3_FN_DLY_RESERVED_DATA_INCDEC_DLY_R(reg) WBGEN2_GEN_READ(reg, 26, 6)
/* definitions for register: Channel 3 fine delay selection */
/* definitions for field: LINE in reg: Channel 3 fine delay selection */
#define WB_FMC_250M_4CH_CSR_CH3_FN_SEL_LINE_MASK WBGEN2_GEN_MASK(0, 17)
#define WB_FMC_250M_4CH_CSR_CH3_FN_SEL_LINE_SHIFT 0
#define WB_FMC_250M_4CH_CSR_CH3_FN_SEL_LINE_W(value) WBGEN2_GEN_WRITE(value, 0, 17)
#define WB_FMC_250M_4CH_CSR_CH3_FN_SEL_LINE_R(reg) WBGEN2_GEN_READ(reg, 0, 17)
/* definitions for field: Reserved in reg: Channel 3 fine delay selection */
#define WB_FMC_250M_4CH_CSR_CH3_FN_SEL_RESERVED_MASK WBGEN2_GEN_MASK(17, 15)
#define WB_FMC_250M_4CH_CSR_CH3_FN_SEL_RESERVED_SHIFT 17
#define WB_FMC_250M_4CH_CSR_CH3_FN_SEL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 17, 15)
#define WB_FMC_250M_4CH_CSR_CH3_FN_SEL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 17, 15)
/* definitions for register: Channel 3 coarse delay register */
/* definitions for field: Falling edge data delay in reg: Channel 3 coarse delay register */
......@@ -461,26 +517,34 @@
#define WB_FMC_250M_4CH_CSR_REG_CH0_STA 0x00000008
/* [0xc]: REG Channel 0 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH0_FN_DLY 0x0000000c
/* [0x10]: REG Channel 0 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH0_CS_DLY 0x00000010
/* [0x14]: REG Channel 1 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH1_STA 0x00000014
/* [0x18]: REG Channel 1 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH1_FN_DLY 0x00000018
/* [0x1c]: REG Channel 1 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH1_CS_DLY 0x0000001c
/* [0x20]: REG Channel 2 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH2_STA 0x00000020
/* [0x24]: REG Channel 2 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH2_FN_DLY 0x00000024
/* [0x28]: REG Channel 2 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH2_CS_DLY 0x00000028
/* [0x2c]: REG Channel 3 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH3_STA 0x0000002c
/* [0x30]: REG Channel 3 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH3_FN_DLY 0x00000030
/* [0x34]: REG Channel 3 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH3_CS_DLY 0x00000034
/* [0x38]: REG FMC temperature monitor register */
#define WB_FMC_250M_4CH_CSR_REG_TEMP 0x00000038
/* [0x10]: REG Channel 0 fine delay selection */
#define WB_FMC_250M_4CH_CSR_REG_CH0_FN_SEL 0x00000010
/* [0x14]: REG Channel 0 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH0_CS_DLY 0x00000014
/* [0x18]: REG Channel 1 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH1_STA 0x00000018
/* [0x1c]: REG Channel 1 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH1_FN_DLY 0x0000001c
/* [0x20]: REG Channel 1 fine delay selection */
#define WB_FMC_250M_4CH_CSR_REG_CH1_FN_SEL 0x00000020
/* [0x24]: REG Channel 1 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH1_CS_DLY 0x00000024
/* [0x28]: REG Channel 2 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH2_STA 0x00000028
/* [0x2c]: REG Channel 2 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH2_FN_DLY 0x0000002c
/* [0x30]: REG Channel 2 fine delay selection */
#define WB_FMC_250M_4CH_CSR_REG_CH2_FN_SEL 0x00000030
/* [0x34]: REG Channel 2 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH2_CS_DLY 0x00000034
/* [0x38]: REG Channel 3 status register */
#define WB_FMC_250M_4CH_CSR_REG_CH3_STA 0x00000038
/* [0x3c]: REG Channel 3 fine delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH3_FN_DLY 0x0000003c
/* [0x40]: REG Channel 3 fine delay selection */
#define WB_FMC_250M_4CH_CSR_REG_CH3_FN_SEL 0x00000040
/* [0x44]: REG Channel 3 coarse delay register */
#define WB_FMC_250M_4CH_CSR_REG_CH3_CS_DLY 0x00000044
/* [0x48]: REG FMC temperature monitor register */
#define WB_FMC_250M_4CH_CSR_REG_TEMP 0x00000048
#endif
hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wbgen/wb_fmc250m_4ch_regs.wb
View file @ 8b3d9071
......@@ -306,6 +306,32 @@ peripheral {
};
};
reg {
name = "Channel 0 fine delay selection";
prefix = "ch0_fn_sel";
field {
name = "LINE";
prefix = "line";
description = "IDELAY Line to update tap value (multiple lines at one can be set), \
including clock line, bit 16 - clk, bits 15-0 - data";
type = SLV;
size = 17;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on write, read as 0's";
prefix = "reserved";
type = SLV;
size = 15;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Channel 0 coarse delay register";
prefix = "ch0_cs_dly";
......@@ -516,6 +542,32 @@ peripheral {
};
};
reg {
name = "Channel 1 fine delay selection";
prefix = "ch1_fn_sel";
field {
name = "LINE";
prefix = "line";
description = "IDELAY Line to update tap value (multiple lines at one can be set), \
including clock line, bit 16 - clk, bits 15-0 - data";
type = SLV;
size = 17;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on write, read as 0's";
prefix = "reserved";
type = SLV;
size = 15;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Channel 1 coarse delay register";
prefix = "ch1_cs_dly";
......@@ -725,6 +777,32 @@ peripheral {
};
};
reg {
name = "Channel 2 fine delay selection";
prefix = "ch2_fn_sel";
field {
name = "LINE";
prefix = "line";
description = "IDELAY Line to update tap value (multiple lines at one can be set), \
including clock line, bit 16 - clk, bits 15-0 - data";
type = SLV;
size = 17;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on write, read as 0's";
prefix = "reserved";
type = SLV;
size = 15;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Channel 2 coarse delay register";
prefix = "ch2_cs_dly";
......@@ -934,6 +1012,32 @@ peripheral {
};
};
reg {
name = "Channel 3 fine delay selection";
prefix = "ch3_fn_sel";
field {
name = "LINE";
prefix = "line";
description = "IDELAY Line to update tap value (multiple lines at one can be set), \
including clock line, bit 16 - clk, bits 15-0 - data";
type = SLV;
size = 17;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on write, read as 0's";
prefix = "reserved";
type = SLV;
size = 15;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Channel 3 coarse delay register";
prefix = "ch3_cs_dly";
......
hdl/sim/regs/wb_fmc250m_4ch_regs.vh
View file @ 8b3d9071
`define ADDR_WB_FMC_250M_4CH_CSR_ADC_STA 6'h0
`define ADDR_WB_FMC_250M_4CH_CSR_ADC_STA 7'h0
`define WB_FMC_250M_4CH_CSR_ADC_STA_CLK_CHAINS_OFFSET 0
`define WB_FMC_250M_4CH_CSR_ADC_STA_CLK_CHAINS 32'h0000000f
`define WB_FMC_250M_4CH_CSR_ADC_STA_RESERVED_CLK_CHAINS_OFFSET 4
......@@ -9,7 +9,7 @@
`define WB_FMC_250M_4CH_CSR_ADC_STA_RESERVED_DATA_CHAINS 32'h0000f000
`define WB_FMC_250M_4CH_CSR_ADC_STA_ADC_PKT_SIZE_OFFSET 16
`define WB_FMC_250M_4CH_CSR_ADC_STA_ADC_PKT_SIZE 32'hffff0000
`define ADDR_WB_FMC_250M_4CH_CSR_ADC_CTL 6'h4
`define ADDR_WB_FMC_250M_4CH_CSR_ADC_CTL 7'h4
`define WB_FMC_250M_4CH_CSR_ADC_CTL_UPDATE_CLK_DLY_OFFSET 0
`define WB_FMC_250M_4CH_CSR_ADC_CTL_UPDATE_CLK_DLY 32'h00000001
`define WB_FMC_250M_4CH_CSR_ADC_CTL_UPDATE_DATA_DLY_OFFSET 1
......@@ -22,12 +22,12 @@
`define WB_FMC_250M_4CH_CSR_ADC_CTL_SLEEP_ADCS 32'h00000010
`define WB_FMC_250M_4CH_CSR_ADC_CTL_RESERVED_OFFSET 5
`define WB_FMC_250M_4CH_CSR_ADC_CTL_RESERVED 32'hffffffe0
`define ADDR_WB_FMC_250M_4CH_CSR_CH0_STA 6'h8
`define ADDR_WB_FMC_250M_4CH_CSR_CH0_STA 7'h8
`define WB_FMC_250M_4CH_CSR_CH0_STA_VAL_OFFSET 0
`define WB_FMC_250M_4CH_CSR_CH0_STA_VAL 32'h0000ffff
`define WB_FMC_250M_4CH_CSR_CH0_STA_RESERVED_OFFSET 16
`define WB_FMC_250M_4CH_CSR_CH0_STA_RESERVED 32'hffff0000
`define ADDR_WB_FMC_250M_4CH_CSR_CH0_FN_DLY 6'hc
`define ADDR_WB_FMC_250M_4CH_CSR_CH0_FN_DLY 7'hc
`define WB_FMC_250M_4CH_CSR_CH0_FN_DLY_CLK_CHAIN_DLY_OFFSET 0
`define WB_FMC_250M_4CH_CSR_CH0_FN_DLY_CLK_CHAIN_DLY 32'h0000001f
`define WB_FMC_250M_4CH_CSR_CH0_FN_DLY_RESERVED_CLK_CHAIN_DLY_OFFSET 5
......@@ -48,7 +48,12 @@
`define WB_FMC_250M_4CH_CSR_CH0_FN_DLY_DEC_DATA_CHAIN_DLY 32'h02000000
`define WB_FMC_250M_4CH_CSR_CH0_FN_DLY_RESERVED_DATA_INCDEC_DLY_OFFSET 26
`define WB_FMC_250M_4CH_CSR_CH0_FN_DLY_RESERVED_DATA_INCDEC_DLY 32'hfc000000
`define ADDR_WB_FMC_250M_4CH_CSR_CH0_CS_DLY 6'h10
`define ADDR_WB_FMC_250M_4CH_CSR_CH0_FN_SEL 7'h10
`define WB_FMC_250M_4CH_CSR_CH0_FN_SEL_LINE_OFFSET 0
`define WB_FMC_250M_4CH_CSR_CH0_FN_SEL_LINE 32'h0001ffff
`define WB_FMC_250M_4CH_CSR_CH0_FN_SEL_RESERVED_OFFSET 17
`define WB_FMC_250M_4CH_CSR_CH0_FN_SEL_RESERVED 32'hfffe0000
`define ADDR_WB_FMC_250M_4CH_CSR_CH0_CS_DLY 7'h14
`define WB_FMC_250M_4CH_CSR_CH0_CS_DLY_FE_DLY_OFFSET 0
`define WB_FMC_250M_4CH_CSR_CH0_CS_DLY_FE_DLY 32'h00000003
`define WB_FMC_250M_4CH_CSR_CH0_CS_DLY_RESERVED_FE_DLY_OFFSET 2
......@@ -57,12 +62,12 @@
`define WB_FMC_250M_4CH_CSR_CH0_CS_DLY_RG_DLY 32'h00000300
`define WB_FMC_250M_4CH_CSR_CH0_CS_DLY_RESERVED_RG_DLY_OFFSET 10
`define WB_FMC_250M_4CH_CSR_CH0_CS_DLY_RESERVED_RG_DLY 32'hfffffc00
`define ADDR_WB_FMC_250M_4CH_CSR_CH1_STA 6'h14
`define ADDR_WB_FMC_250M_4CH_CSR_CH1_STA 7'h18
`define WB_FMC_250M_4CH_CSR_CH1_STA_VAL_OFFSET 0
`define WB_FMC_250M_4CH_CSR_CH1_STA_VAL 32'h0000ffff
`define WB_FMC_250M_4CH_CSR_CH1_STA_RESERVED_OFFSET 16
`define WB_FMC_250M_4CH_CSR_CH1_STA_RESERVED 32'hffff0000
`define ADDR_WB_FMC_250M_4CH_CSR_CH1_FN_DLY 6'h18
`define ADDR_WB_FMC_250M_4CH_CSR_CH1_FN_DLY 7'h1c
`define WB_FMC_250M_4CH_CSR_CH1_FN_DLY_CLK_CHAIN_DLY_OFFSET 0
`define WB_FMC_250M_4CH_CSR_CH1_FN_DLY_CLK_CHAIN_DLY 32'h0000001f
`define WB_FMC_250M_4CH_CSR_CH1_FN_DLY_RESERVED_CLK_CHAIN_DLY_OFFSET 5
......@@ -83,7 +88,12 @@
`define WB_FMC_250M_4CH_CSR_CH1_FN_DLY_DEC_DATA_CHAIN_DLY 32'h02000000
`define WB_FMC_250M_4CH_CSR_CH1_FN_DLY_RESERVED_DATA_INCDEC_DLY_OFFSET 26
`define WB_FMC_250M_4CH_CSR_CH1_FN_DLY_RESERVED_DATA_INCDEC_DLY 32'hfc000000
`define ADDR_WB_FMC_250M_4CH_CSR_CH1_CS_DLY 6'h1c
`define ADDR_WB_FMC_250M_4CH_CSR_CH1_FN_SEL 7'h20
`define WB_FMC_250M_4CH_CSR_CH1_FN_SEL_LINE_OFFSET 0
`define WB_FMC_250M_4CH_CSR_CH1_FN_SEL_LINE 32'h0001ffff
`define WB_FMC_250M_4CH_CSR_CH1_FN_SEL_RESERVED_OFFSET 17
`define WB_FMC_250M_4CH_CSR_CH1_FN_SEL_RESERVED 32'hfffe0000
`define ADDR_WB_FMC_250M_4CH_CSR_CH1_CS_DLY 7'h24
`define WB_FMC_250M_4CH_CSR_CH1_CS_DLY_FE_DLY_OFFSET 0
`define WB_FMC_250M_4CH_CSR_CH1_CS_DLY_FE_DLY 32'h00000003
`define WB_FMC_250M_4CH_CSR_CH1_CS_DLY_RESERVED_FE_DLY_OFFSET 2
......@@ -92,12 +102,12 @@
`define WB_FMC_250M_4CH_CSR_CH1_CS_DLY_RG_DLY 32'h00000300
`define WB_FMC_250M_4CH_CSR_CH1_CS_DLY_RESERVED_RG_DLY_OFFSET 10
`define WB_FMC_250M_4CH_CSR_CH1_CS_DLY_RESERVED_RG_DLY 32'hfffffc00
`define ADDR_WB_FMC_250M_4CH_CSR_CH2_STA 6'h20
`define ADDR_WB_FMC_250M_4CH_CSR_CH2_STA 7'h28
`define WB_FMC_250M_4CH_CSR_CH2_STA_VAL_OFFSET 0
`define WB_FMC_250M_4CH_CSR_CH2_STA_VAL 32'h0000ffff
`define WB_FMC_250M_4CH_CSR_CH2_STA_RESERVED_OFFSET 16
`define WB_FMC_250M_4CH_CSR_CH2_STA_RESERVED 32'hffff0000
`define ADDR_WB_FMC_250M_4CH_CSR_CH2_FN_DLY 6'h24
`define ADDR_WB_FMC_250M_4CH_CSR_CH2_FN_DLY 7'h2c
`define WB_FMC_250M_4CH_CSR_CH2_FN_DLY_CLK_CHAIN_DLY_OFFSET 0
`define WB_FMC_250M_4CH_CSR_CH2_FN_DLY_CLK_CHAIN_DLY 32'h0000001f
`define WB_FMC_250M_4CH_CSR_CH2_FN_DLY_RESERVED_CLK_CHAIN_DLY_OFFSET 5
......@@ -118,7 +128,12 @@
`define WB_FMC_250M_4CH_CSR_CH2_FN_DLY_DEC_DATA_CHAIN_DLY 32'h02000000
`define WB_FMC_250M_4CH_CSR_CH2_FN_DLY_RESERVED_DATA_INCDEC_DLY_OFFSET 26
`define WB_FMC_250M_4CH_CSR_CH2_FN_DLY_RESERVED_DATA_INCDEC_DLY 32'hfc000000
`define ADDR_WB_FMC_250M_4CH_CSR_CH2_CS_DLY 6'h28
`define ADDR_WB_FMC_250M_4CH_CSR_CH2_FN_SEL 7'h30
`define WB_FMC_250M_4CH_CSR_CH2_FN_SEL_LINE_OFFSET 0
`define WB_FMC_250M_4CH_CSR_CH2_FN_SEL_LINE 32'h0001ffff
`define WB_FMC_250M_4CH_CSR_CH2_FN_SEL_RESERVED_OFFSET 17
`define WB_FMC_250M_4CH_CSR_CH2_FN_SEL_RESERVED 32'hfffe0000
`define ADDR_WB_FMC_250M_4CH_CSR_CH2_CS_DLY 7'h34
`define WB_FMC_250M_4CH_CSR_CH2_CS_DLY_FE_DLY_OFFSET 0
`define WB_FMC_250M_4CH_CSR_CH2_CS_DLY_FE_DLY 32'h00000003
`define WB_FMC_250M_4CH_CSR_CH2_CS_DLY_RESERVED_FE_DLY_OFFSET 2
......@@ -127,12 +142,12 @@
`define WB_FMC_250M_4CH_CSR_CH2_CS_DLY_RG_DLY 32'h00000300
`define WB_FMC_250M_4CH_CSR_CH2_CS_DLY_RESERVED_RG_DLY_OFFSET 10
`define WB_FMC_250M_4CH_CSR_CH2_CS_DLY_RESERVED_RG_DLY 32'hfffffc00
`define ADDR_WB_FMC_250M_4CH_CSR_CH3_STA 6'h2c
`define ADDR_WB_FMC_250M_4CH_CSR_CH3_STA 7'h38
`define WB_FMC_250M_4CH_CSR_CH3_STA_VAL_OFFSET 0
`define WB_FMC_250M_4CH_CSR_CH3_STA_VAL 32'h0000ffff
`define WB_FMC_250M_4CH_CSR_CH3_STA_RESERVED_OFFSET 16
`define WB_FMC_250M_4CH_CSR_CH3_STA_RESERVED 32'hffff0000
`define ADDR_WB_FMC_250M_4CH_CSR_CH3_FN_DLY 6'h30
`define ADDR_WB_FMC_250M_4CH_CSR_CH3_FN_DLY 7'h3c
`define WB_FMC_250M_4CH_CSR_CH3_FN_DLY_CLK_CHAIN_DLY_OFFSET 0
`define WB_FMC_250M_4CH_CSR_CH3_FN_DLY_CLK_CHAIN_DLY 32'h0000001f
`define WB_FMC_250M_4CH_CSR_CH3_FN_DLY_RESERVED_CLK_CHAIN_DLY_OFFSET 5
......@@ -153,7 +168,12 @@
`define WB_FMC_250M_4CH_CSR_CH3_FN_DLY_DEC_DATA_CHAIN_DLY 32'h02000000
`define WB_FMC_250M_4CH_CSR_CH3_FN_DLY_RESERVED_DATA_INCDEC_DLY_OFFSET 26
`define WB_FMC_250M_4CH_CSR_CH3_FN_DLY_RESERVED_DATA_INCDEC_DLY 32'hfc000000
`define ADDR_WB_FMC_250M_4CH_CSR_CH3_CS_DLY 6'h34
`define ADDR_WB_FMC_250M_4CH_CSR_CH3_FN_SEL 7'h40
`define WB_FMC_250M_4CH_CSR_CH3_FN_SEL_LINE_OFFSET 0
`define WB_FMC_250M_4CH_CSR_CH3_FN_SEL_LINE 32'h0001ffff
`define WB_FMC_250M_4CH_CSR_CH3_FN_SEL_RESERVED_OFFSET 17
`define WB_FMC_250M_4CH_CSR_CH3_FN_SEL_RESERVED 32'hfffe0000
`define ADDR_WB_FMC_250M_4CH_CSR_CH3_CS_DLY 7'h44
`define WB_FMC_250M_4CH_CSR_CH3_CS_DLY_FE_DLY_OFFSET 0
`define WB_FMC_250M_4CH_CSR_CH3_CS_DLY_FE_DLY 32'h00000003
`define WB_FMC_250M_4CH_CSR_CH3_CS_DLY_RESERVED_FE_DLY_OFFSET 2
......@@ -162,6 +182,6 @@
`define WB_FMC_250M_4CH_CSR_CH3_CS_DLY_RG_DLY 32'h00000300
`define WB_FMC_250M_4CH_CSR_CH3_CS_DLY_RESERVED_RG_DLY_OFFSET 10
`define WB_FMC_250M_4CH_CSR_CH3_CS_DLY_RESERVED_RG_DLY 32'hfffffc00
`define ADDR_WB_FMC_250M_4CH_CSR_TEMP 6'h38
`define ADDR_WB_FMC_250M_4CH_CSR_TEMP 7'h48
`define WB_FMC_250M_4CH_CSR_TEMP_MON_DEV_OFFSET 0
`define WB_FMC_250M_4CH_CSR_TEMP_MON_DEV 32'h00000001
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