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Beam Positoning Monitor - Gateware
Commit 8b84e235 authored by Adrian Byszuk's avatar Adrian Byszuk
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Change HDL code to support new AXI infrastructure. 

Also some minor changes:
- remove device specific bpm_pcie_a7/bpm_pcie_k7 wrappers. Now a single
  bpm_pcie.vhd file is enough, as it includes ipcores_pkg.vhd package
  with necessary device-specific constraints.
- remove bpm_pcie_* packages. User design can simply use
    module_inst: entity work.module
  instantiation style
- change wb_transact to comply with native FIFO36E1 reset DRC
- nuke ML605 support
- remove unused HDL modules
- fix some regs to use synchronous reset. More to follow.
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hdl/modules/pcie/Manifest.py
View file @ 8b84e235
files = ["bpm_pcie_a7.vhd",
"bpm_pcie_k7.vhd",
"bpm_pcie_ml605.vhd",
"bpm_pcie_a7_priv_pkg.vhd",
"bpm_pcie_k7_priv_pkg.vhd",
"bpm_pcie_ml605_priv_pkg.vhd",
"bpm_pcie_a7_const_pkg.vhd",
"bpm_pcie_k7_const_pkg.vhd",
"bpm_pcie_ml605_const_pkg.vhd"
files = ["bpm_pcie.vhd",
]
modules = {"local" : ["common"],
modules = {"local" : ["common/", "pkgs/"],
"git" : ["https://github.com/lerwys/general-cores.git"]}
# original version hosted at OHWR:
# "git" : ["git://ohwr.org/hdl-core-lib/general-cores.git"]}
......
hdl/modules/pcie/bpm_pcie.vhd 0 → 100644
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hdl/modules/pcie/bpm_pcie_a7.vhd deleted 100644 → 0
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hdl/modules/pcie/bpm_pcie_a7_const_pkg.vhd deleted 100644 → 0
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library ieee;
use ieee.std_logic_1164.all;
package bpm_pcie_a7_const_pkg is
--------------------------------------------------------------------
-- Constants
--------------------------------------------------------------------
-- PCIe Lanes
constant c_pcie_lanes : integer := 4;
-- PCIE Constants from Xilinx COREGEN
constant c_ddr_dq_width : integer := 32;
constant c_ddr_payload_width : integer := 256;
constant c_ddr_dqs_width : integer := 4;
constant c_ddr_dm_width : integer := 4;
constant c_ddr_row_width : integer := 16;
constant c_ddr_bank_width : integer := 3;
constant c_ddr_ck_width : integer := 1;
constant c_ddr_cke_width : integer := 1;
constant c_ddr_odt_width : integer := 1;
constant c_ddr_addr_width : integer := 30;
end bpm_pcie_a7_const_pkg;
hdl/modules/pcie/bpm_pcie_a7_priv_pkg.vhd deleted 100644 → 0
View file @ 288ab640
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.abb64Package.all;
use work.wishbone_pkg.all;
package bpm_pcie_a7_priv_pkg is
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component bpm_pcie_a7
generic (
SIMULATION : string := "FALSE";
EXT_RST_PIN : boolean := true;
-- ****
-- PCIe core parameters
-- ****
constant pcieLanes : integer := 4;
PL_FAST_TRAIN : string := "FALSE";
PIPE_SIM_MODE : string := "FALSE";
--***************************************************************************
-- Necessary parameters for DDR core support
-- (dependent on memory chip connected to FPGA, not to be modified at will)
--***************************************************************************
constant DDR_DQ_WIDTH : integer := 32;
constant DDR_PAYLOAD_WIDTH : integer := 256;
constant DDR_DQS_WIDTH : integer := 4;
constant DDR_DM_WIDTH : integer := 4;
constant DDR_ROW_WIDTH : integer := 16;
constant DDR_BANK_WIDTH : integer := 3;
constant DDR_CK_WIDTH : integer := 1;
constant DDR_CKE_WIDTH : integer := 1;
constant DDR_ODT_WIDTH : integer := 1;
SIM_BYPASS_INIT_CAL : string := "FAST"
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
);
port (
--DDR3 memory pins
ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_rxn : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txp : out std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txn : out std_logic_vector(pcieLanes - 1 downto 0);
-- Necessity signals
ddr_sys_clk_p : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL)
ddr_sys_clk_n : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL)
sys_clk_p : in std_logic; --100 MHz PCIe Clock (connect directly to input pin)
sys_clk_n : in std_logic; --100 MHz PCIe Clock
sys_rst_n : in std_logic; --Reset to PCIe core
-- DDR memory controller interface --
ddr_core_rst : in std_logic;
memc_ui_clk : out std_logic;
memc_ui_rst : out std_logic;
memc_cmd_rdy : out std_logic;
memc_cmd_en : in std_logic;
memc_cmd_instr : in std_logic_vector(2 downto 0);
memc_cmd_addr : in std_logic_vector(31 downto 0);
memc_wr_en : in std_logic;
memc_wr_end : in std_logic;
memc_wr_mask : in std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
memc_wr_data : in std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_wr_rdy : out std_logic;
memc_rd_data : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_rd_valid : out std_logic;
---- memory arbiter interface
memarb_acc_req : in std_logic;
memarb_acc_gnt : out std_logic;
--/ DDR memory controller interface
-- Wishbone interface --
CLK_I : in std_logic;
RST_I : in std_logic;
ACK_I : in std_logic;
DAT_I : in std_logic_vector(63 downto 0);
ADDR_O : out std_logic_vector(28 downto 0);
DAT_O : out std_logic_vector(63 downto 0);
WE_O : out std_logic;
STB_O : out std_logic;
SEL_O : out std_logic;
CYC_O : out std_logic;
--/ Wishbone interface
-- Additional exported signals for instantiation
ext_rst_o : out std_logic;
-- Debug signals
dbg_app_addr_o : out std_logic_vector(31 downto 0);
dbg_app_cmd_o : out std_logic_vector(2 downto 0);
dbg_app_en_o : out std_logic;
dbg_app_wdf_data_o : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
dbg_app_wdf_end_o : out std_logic;
dbg_app_wdf_wren_o : out std_logic;
dbg_app_wdf_mask_o : out std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
dbg_app_rd_data_o : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
dbg_app_rd_data_end_o : out std_logic;
dbg_app_rd_data_valid_o : out std_logic;
dbg_app_rdy_o : out std_logic;
dbg_app_wdf_rdy_o : out std_logic;
dbg_ddr_ui_clk_o : out std_logic;
dbg_ddr_ui_reset_o : out std_logic;
dbg_arb_req_o : out std_logic_vector(1 downto 0);
dbg_arb_gnt_o : out std_logic_vector(1 downto 0)
);
end component;
end bpm_pcie_a7_priv_pkg;
hdl/modules/pcie/bpm_pcie_k7.vhd deleted 100644 → 0
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hdl/modules/pcie/bpm_pcie_k7_const_pkg.vhd deleted 100644 → 0
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library ieee;
use ieee.std_logic_1164.all;
package bpm_pcie_k7_const_pkg is
--------------------------------------------------------------------
-- Constants
--------------------------------------------------------------------
-- PCIe Lanes
constant c_pcie_lanes : integer := 4;
-- PCIE Constants from Xilinx COREGEN
constant c_ddr_dq_width : integer := 64;
constant c_ddr_payload_width : integer := 512;
constant c_ddr_dqs_width : integer := 8;
constant c_ddr_dm_width : integer := 8;
constant c_ddr_row_width : integer := 14;
constant c_ddr_bank_width : integer := 3;
constant c_ddr_ck_width : integer := 1;
constant c_ddr_cke_width : integer := 1;
constant c_ddr_odt_width : integer := 1;
constant c_ddr_addr_width : integer := 28;
end bpm_pcie_k7_const_pkg;
hdl/modules/pcie/bpm_pcie_k7_priv_pkg.vhd deleted 100644 → 0
View file @ 288ab640
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.abb64Package.all;
use work.wishbone_pkg.all;
package bpm_pcie_k7_priv_pkg is
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component bpm_pcie_k7
generic (
SIMULATION : string := "FALSE";
-- ****
-- PCIe core parameters
-- ****
constant pcieLanes : integer := 4;
PL_FAST_TRAIN : string := "FALSE";
PIPE_SIM_MODE : string := "FALSE";
--***************************************************************************
-- Necessary parameters for DDR core support
-- (dependent on memory chip connected to FPGA, not to be modified at will)
--***************************************************************************
constant DDR_DQ_WIDTH : integer := 64;
constant DDR_PAYLOAD_WIDTH : integer := 512;
constant DDR_DQS_WIDTH : integer := 8;
constant DDR_DM_WIDTH : integer := 8;
constant DDR_ROW_WIDTH : integer := 14;
constant DDR_BANK_WIDTH : integer := 3;
constant DDR_CK_WIDTH : integer := 1;
constant DDR_CKE_WIDTH : integer := 1;
constant DDR_ODT_WIDTH : integer := 1;
SIM_BYPASS_INIT_CAL : string := "FAST"
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
);
port (
--DDR3 memory pins
ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_rxn : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txp : out std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txn : out std_logic_vector(pcieLanes - 1 downto 0);
-- Necessity signals
ddr_sys_clk_p : in std_logic;
ddr_sys_clk_n : in std_logic;
sys_clk_p : in std_logic; --100 MHz PCIe Clock
sys_clk_n : in std_logic; --100 MHz PCIe Clock
sys_rst_n : in std_logic; --Reset to PCIe core
-- DDR memory controller interface --
-- uncomment when instantiating in another project
ddr_core_rst : in std_logic;
memc_ui_clk : out std_logic;
memc_ui_rst : out std_logic;
memc_cmd_rdy : out std_logic;
memc_cmd_en : in std_logic;
memc_cmd_instr : in std_logic_vector(2 downto 0);
memc_cmd_addr : in std_logic_vector(31 downto 0);
memc_wr_en : in std_logic;
memc_wr_end : in std_logic;
memc_wr_mask : in std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
memc_wr_data : in std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_wr_rdy : out std_logic;
memc_rd_data : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_rd_valid : out std_logic;
-- memory arbiter interface
memarb_acc_req : in std_logic;
memarb_acc_gnt : out std_logic;
--/ DDR memory controller interface
-- Wishbone interface --
-- uncomment when instantiating in another project
CLK_I : in std_logic;
RST_I : in std_logic;
ACK_I : in std_logic;
DAT_I : in std_logic_vector(63 downto 0);
ADDR_O : out std_logic_vector(28 downto 0);
DAT_O : out std_logic_vector(63 downto 0);
WE_O : out std_logic;
STB_O : out std_logic;
SEL_O : out std_logic;
CYC_O : out std_logic;
--/ Wishbone interface
-- Additional exported signals for instantiation
ext_rst_o : out std_logic
);
end component;
end bpm_pcie_k7_priv_pkg;
hdl/modules/pcie/bpm_pcie_ml605.vhd deleted 100644 → 0
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hdl/modules/pcie/bpm_pcie_ml605_const_pkg.vhd deleted 100644 → 0
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library ieee;
use ieee.std_logic_1164.all;
package bpm_pcie_ml605_const_pkg is
--------------------------------------------------------------------
-- Constants
--------------------------------------------------------------------
-- PCIe Lanes
constant c_pcie_lanes : integer := 4;
-- PCIE Constants from Xilinx COREGEN
constant c_ddr_dq_width : integer := 64;
constant c_ddr_payload_width : integer := 256;
constant c_ddr_dqs_width : integer := 8;
constant c_ddr_dm_width : integer := 8;
constant c_ddr_row_width : integer := 14;
constant c_ddr_bank_width : integer := 3;
constant c_ddr_ck_width : integer := 1;
constant c_ddr_cke_width : integer := 1;
constant c_ddr_odt_width : integer := 1;
constant c_ddr_addr_width : integer := 28;
end bpm_pcie_ml605_const_pkg;
hdl/modules/pcie/bpm_pcie_ml605_priv_pkg.vhd deleted 100644 → 0
View file @ 288ab640
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.abb64Package.all;
use work.wishbone_pkg.all;
package bpm_pcie_ml605_priv_pkg is
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component bpm_pcie_ml605
generic (
SIMULATION : string := "FALSE";
-- ****
-- PCIe core parameters
-- ****
constant pcieLanes : integer := 4;
PL_FAST_TRAIN : string := "FALSE";
PIPE_SIM_MODE : string := "FALSE";
--***************************************************************************
-- Necessary parameters for DDR core support
-- (dependent on memory chip connected to FPGA, not to be modified at will)
--***************************************************************************
constant DDR_DQ_WIDTH : integer := 64;
constant DDR_PAYLOAD_WIDTH : integer := 256;
constant DDR_DQS_WIDTH : integer := 8;
constant DDR_DM_WIDTH : integer := 8;
constant DDR_ROW_WIDTH : integer := 14;
constant DDR_BANK_WIDTH : integer := 3;
constant DDR_CK_WIDTH : integer := 1;
constant DDR_CKE_WIDTH : integer := 1;
constant DDR_ODT_WIDTH : integer := 1;
SIM_BYPASS_INIT_CAL : string := "FAST"
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
);
port (
--DDR3 memory pins
ddr3_dq : inout std_logic_vector(DDR_DQ_WIDTH-1 downto 0);
ddr3_dqs_p : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_dqs_n : inout std_logic_vector(DDR_DQS_WIDTH-1 downto 0);
ddr3_addr : out std_logic_vector(DDR_ROW_WIDTH-1 downto 0);
ddr3_ba : out std_logic_vector(DDR_BANK_WIDTH-1 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_ck_n : out std_logic_vector(DDR_CK_WIDTH-1 downto 0);
ddr3_cke : out std_logic_vector(DDR_CKE_WIDTH-1 downto 0);
ddr3_dm : out std_logic_vector(DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(DDR_ODT_WIDTH-1 downto 0);
-- PCIe transceivers
pci_exp_rxp : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_rxn : in std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txp : out std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txn : out std_logic_vector(pcieLanes - 1 downto 0);
-- Necessity signals
ddr_sys_clk_p : in std_logic; --200 MHz DDR core clock (connect through BUFG or PLL)
sys_clk_p : in std_logic; --100 MHz PCIe Clock (connect directly to input pin)
sys_clk_n : in std_logic; --100 MHz PCIe Clock
sys_rst_n : in std_logic; --Reset to PCIe core
-- DDR memory controller interface --
-- uncomment when instantiating in another project
ddr_core_rst : in std_logic;
memc_ui_clk : out std_logic;
memc_ui_rst : out std_logic;
memc_cmd_rdy : out std_logic;
memc_cmd_en : in std_logic;
memc_cmd_instr : in std_logic_vector(2 downto 0);
memc_cmd_addr : in std_logic_vector(31 downto 0);
memc_wr_en : in std_logic;
memc_wr_end : in std_logic;
memc_wr_mask : in std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
memc_wr_data : in std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_wr_rdy : out std_logic;
memc_rd_data : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
memc_rd_valid : out std_logic;
---- memory arbiter interface
memarb_acc_req : in std_logic;
memarb_acc_gnt : out std_logic;
--/ DDR memory controller interface
-- Wishbone interface --
-- uncomment when instantiating in another project
CLK_I : in std_logic;
RST_I : in std_logic;
ACK_I : in std_logic;
DAT_I : in std_logic_vector(63 downto 0);
ADDR_O : out std_logic_vector(28 downto 0);
DAT_O : out std_logic_vector(63 downto 0);
WE_O : out std_logic;
STB_O : out std_logic;
SEL_O : out std_logic;
CYC_O : out std_logic;
--/ Wishbone interface
-- Additional exported signals for instantiation
ext_rst_o : out std_logic;
-- Debug signals
dbg_app_addr_o : out std_logic_vector(31 downto 0);
dbg_app_cmd_o : out std_logic_vector(2 downto 0);
dbg_app_en_o : out std_logic;
dbg_app_wdf_data_o : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
dbg_app_wdf_end_o : out std_logic;
dbg_app_wdf_wren_o : out std_logic;
dbg_app_wdf_mask_o : out std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
dbg_app_rd_data_o : out std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
dbg_app_rd_data_end_o : out std_logic;
dbg_app_rd_data_valid_o : out std_logic;
dbg_app_rdy_o : out std_logic;
dbg_app_wdf_rdy_o : out std_logic;
dbg_ddr_ui_clk_o : out std_logic;
dbg_ddr_ui_reset_o : out std_logic;
dbg_arb_req_o : out std_logic_vector(1 downto 0);
dbg_arb_gnt_o : out std_logic_vector(1 downto 0)
);
end component;
end bpm_pcie_ml605_priv_pkg;
hdl/modules/pcie/common/DDR_Blinker.vhd deleted 100644 → 0
View file @ 288ab640
----------------------------------------------------------------------------------
-- Company: ZITI
-- Engineer: wgao
--
-- Create Date: 16:38:03 06 Oct 2008
-- Design Name:
-- Module Name: DDR_Blink - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DDR_Blink is
port (
DDR_blinker : out std_logic;
DDR_Write : in std_logic;
DDR_Read : in std_logic;
DDR_Both : in std_logic;
ddr_Clock : in std_logic;
DDr_Rst_n : in std_logic
);
end entity DDR_Blink;
architecture Behavioral of DDR_Blink is
-- Blinking -_-_-_-_
constant C_BLINKER_MSB : integer := 15; -- 4; -- 15;
constant CBIT_SLOW_BLINKER : integer := 11; -- 2; -- 11;
signal DDR_blinker_i : std_logic;
signal Fast_blinker : std_logic_vector(C_BLINKER_MSB downto 0);
signal Fast_blinker_MSB_r1 : std_logic;
signal Blink_Pulse : std_logic;
signal Slow_blinker : std_logic_vector(CBIT_SLOW_BLINKER downto 0);
signal DDR_write_extension : std_logic;
signal DDR_write_extension_Cnt : std_logic_vector(1 downto 0);
signal DDR_read_extension : std_logic;
signal DDR_read_extension_Cnt : std_logic_vector(1 downto 0);
begin
--
Syn_DDR_Fast_blinker :
process (ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
Fast_blinker <= (others => '0');
Fast_blinker_MSB_r1 <= '0';
Blink_Pulse <= '0';
Slow_blinker <= (others => '0');
elsif ddr_Clock'event and ddr_Clock = '1' then
Fast_blinker <= Fast_blinker + '1';
Fast_blinker_MSB_r1 <= Fast_blinker(C_BLINKER_MSB);
Blink_Pulse <= Fast_blinker(C_BLINKER_MSB) and not Fast_blinker_MSB_r1;
Slow_blinker <= Slow_blinker + Blink_Pulse;
end if;
end process;
--
Syn_DDR_Write_Extenstion :
process (ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
DDR_write_extension_Cnt <= (others => '0');
DDR_write_extension <= '0';
elsif ddr_Clock'event and ddr_Clock = '1' then
case DDR_write_extension_Cnt is
when "00" =>
if DDR_Write = '1' then
DDR_write_extension_Cnt <= "01";
DDR_write_extension <= '1';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
when "01" =>
if Slow_blinker(CBIT_SLOW_BLINKER) = '1' then
DDR_write_extension_Cnt <= "11";
DDR_write_extension <= '1';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
when "11" =>
if Slow_blinker(CBIT_SLOW_BLINKER) = '0' then
DDR_write_extension_Cnt <= "10";
DDR_write_extension <= '1';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
when others =>
if Slow_blinker(CBIT_SLOW_BLINKER) = '1' then
DDR_write_extension_Cnt <= "00";
DDR_write_extension <= '0';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
end case;
end if;
end process;
--
Syn_DDR_Read_Extenstion :
process (ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
DDR_read_extension_Cnt <= (others => '0');
DDR_read_extension <= '1';
elsif ddr_Clock'event and ddr_Clock = '1' then
case DDR_read_extension_Cnt is
when "00" =>
if DDR_Read = '1' then
DDR_read_extension_Cnt <= "01";
DDR_read_extension <= '0';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
when "01" =>
if Slow_blinker(CBIT_SLOW_BLINKER) = '1' then
DDR_read_extension_Cnt <= "11";
DDR_read_extension <= '0';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
when "11" =>
if Slow_blinker(CBIT_SLOW_BLINKER) = '0' then
DDR_read_extension_Cnt <= "10";
DDR_read_extension <= '0';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
when others =>
if Slow_blinker(CBIT_SLOW_BLINKER) = '1' then
DDR_read_extension_Cnt <= "00";
DDR_read_extension <= '1';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
end case;
end if;
end process;
--
Syn_DDR_Working_blinker :
process (ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
DDR_Blinker_i <= '0';
elsif ddr_Clock'event and ddr_Clock = '1' then
DDR_Blinker_i <= (Slow_blinker(CBIT_SLOW_BLINKER-2) or DDR_write_extension) and DDR_read_extension;
-- DDR_Blinker_i <= Slow_blinker(CBIT_SLOW_BLINKER-2);
end if;
end process;
DDR_blinker <= DDR_blinker_i;
end architecture Behavioral;
hdl/modules/pcie/common/DDRs_Control.vhd deleted 100644 → 0
View file @ 288ab640
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hdl/modules/pcie/common/Manifest.py deleted 100644 → 0
View file @ 288ab640
files = ["v6abb64Package_efifo_elink.vhd",
"DDR_Blinker.vhd",
"DMA_Calculate.vhd",
"DMA_FSM.vhd",
"Interrupts.vhd",
"Registers.vhd",
"RxIn_Delays.vhd",
"Tx_Output_Arbitor.vhd",
"DDRs_Control.vhd",
"bram_DDRs_Control_Loopback.vhd",
"ddr_Transact.vhd",
"rx_CplD_Channel.vhd",
"rx_MRd_Channel.vhd",
"rx_MWr_Channel.vhd",
"rx_Transact.vhd",
"rx_dsDMA_Channel.vhd",
"rx_usDMA_Channel.vhd",
"tlpControl.vhd",
"tx_Mem_Reader.vhd",
"tx_Transact.vhd",
"wb_transact.vhd",
"wb_mem.vhd"]
hdl/modules/pcie/common/Registers.vhd
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hdl/modules/pcie/common/RxIn_Delays.vhd
View file @ 8b84e235
......@@ -47,7 +47,8 @@ entity RxIn_Delay is
m_axis_rx_tvalid : in std_logic;
m_axis_rx_tbar_hit : in std_logic_vector(C_BAR_NUMBER-1 downto 0);
m_axis_rx_tready : out std_logic;
Pool_wrBuf_full : in std_logic;
ddr_s2mm_cmd_tready : in std_logic;
ddr_s2mm_tready : in std_logic;
wb_FIFO_full : in std_logic;
-- Delay for one clock
......@@ -797,11 +798,11 @@ begin
--will hit when *_tready_i = 0 which will cause deadlock
if m_axis_rx_tlast = '1' and m_axis_rx_tvalid = '1' and m_axis_rx_tready_i = '1' then
FSM_TLP_Cnt <= TK_Idle;
m_axis_rx_tready_i <= not(((MWr_on_Pool or CplD_on_Pool_i) and Pool_wrBuf_full)
m_axis_rx_tready_i <= not(((MWr_on_Pool or CplD_on_Pool_i) and not(ddr_s2mm_tready))
or ((MWr_on_EB or CplD_on_EB_i) and wb_fifo_full));
else
FSM_TLP_Cnt <= TK_Body;
m_axis_rx_tready_i <= not(((MWr_on_Pool or CplD_on_Pool_i) and Pool_wrBuf_full)
m_axis_rx_tready_i <= not(((MWr_on_Pool or CplD_on_Pool_i) and not(ddr_s2mm_tready))
or ((MWr_on_EB or CplD_on_EB_i) and wb_fifo_full));
end if;
......
hdl/modules/pcie/common/Tx_Output_Arbitor.vhd
View file @ 8b84e235
......@@ -263,28 +263,28 @@ begin
for i in 0 to C_ARBITRATE_WIDTH-1 generate
Proc_Priority_Cycling :
process (clk, rst_n)
process (clk)
begin
if (rst_n = '0') then
ChPriority(i) <= Prior_Init_Value(i);
elsif clk'event and clk = '1' then
case Arb_FSM is
when aSt_ReadOne =>
if ChPriority(i) = Champion_Vector then
ChPriority(i) <= C_LOWEST_PRIORITY;
elsif (ChPriority(i) and Champion_Vector) = Champion_Vector then
if rising_edge(clk) then
if (rst_n = '0') then
ChPriority(i) <= Prior_Init_Value(i);
else
case Arb_FSM is
when aSt_ReadOne =>
if ChPriority(i) = Champion_Vector then
ChPriority(i) <= C_LOWEST_PRIORITY;
elsif (ChPriority(i) and Champion_Vector) = Champion_Vector then
ChPriority(i) <= ChPriority(i);
else
ChPriority(i) <= ChPriority(i)(C_ARBITRATE_WIDTH-2 downto 0) & '1';
end if;
when others =>
ChPriority(i) <= ChPriority(i);
else
ChPriority(i) <= ChPriority(i)(C_ARBITRATE_WIDTH-2 downto 0) & '1';
end if;
when others =>
ChPriority(i) <= ChPriority(i);
end case;
end case;
end if;
end if;
end process;
......
hdl/modules/pcie/common/bram_DDRs_Control_Loopback.vhd deleted 100644 → 0
View file @ 288ab640
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hdl/modules/pcie/common/ddr_Transact.vhd
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hdl/modules/pcie/common/rx_CplD_Channel.vhd
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hdl/modules/pcie/common/rx_MWr_Channel.vhd
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This diff is collapsed.
hdl/modules/pcie/common/rx_Transact.vhd
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This diff is collapsed.
hdl/modules/pcie/common/tlpControl.vhd
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This diff is collapsed.
hdl/modules/pcie/common/tx_Mem_Reader.vhd
View file @ 8b84e235
This diff is collapsed.
hdl/modules/pcie/common/tx_Transact.vhd
View file @ 8b84e235
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hdl/modules/pcie/common/wb_transact.vhd
View file @ 8b84e235
......@@ -94,7 +94,7 @@ architecture Behavioral of wb_transact is
signal rpipec_wen : std_logic;
signal rpipec_qout : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
signal rpipec_valid : std_logic;
signal rpipec_ren : std_logic;
signal rpipec_ren : std_logic := '0';
signal rpipec_empty : std_logic;
signal rpipec_full : std_logic;
signal rpipec_afull : std_logic;
......@@ -121,10 +121,17 @@ architecture Behavioral of wb_transact is
begin
rst_i <= wb_rst or rst;
rst_rd_i <= rst_i or rd_tout;
rst_n_i <= not rst_i;
rst_rd_n_i <= not rst_rd_i;
process (wb_clk)
begin
-- sync reset signal
if rising_edge(wb_clk) then
rst_i <= wb_rst or rst;
end if;
end process;
--Wishbone interface FSM
WB_fsm :
......@@ -139,6 +146,7 @@ begin
wb_sel <= (others => '0');
wpipe_ren <= '0';
rpiped_we <= '0';
rpipec_ren <= '0';
else
case wb_state is
when st_RESET =>
......
hdl/modules/pcie/common/v6abb64Package_efifo_elink.vhd → hdl/modules/pcie/pkgs/v6abb64Package_efifo_elink.vhd
View file @ 8b84e235
......@@ -12,9 +12,6 @@ use IEEE.STD_LOGIC_ARITH.all;
package abb64Package is
-- Implemet a design with only one FIFO and only one BRAM Module: For Loopback Test!!
constant USE_LOOPBACK_TEST : boolean := false;
-- Declare constants
-- ----------------------------------------------------------------------
......@@ -370,6 +367,11 @@ package abb64Package is
-- Bit range of Wishbone address in Channel Buffer word
constant C_CHBUF_WB_BIT_BOT : integer := C_CHANNEL_BUF_WIDTH-C_WB_AWIDTH; --97;
constant C_CHBUF_WB_BIT_TOP : integer := C_CHANNEL_BUF_WIDTH-1; --127;
------------------------------------------------------------------------
-- TX Mem Reader channel bit definitions
constant C_TXMEM_TLAST_BIT : integer := C_DBUS_WIDTH;
constant C_TXMEM_KEEP_BIT : integer := C_DBUS_WIDTH+6;
------------------------------------------------------------------------
-- The Relaxed Ordering bit constant in TLP
constant C_RELAXED_ORDERING : std_logic := '0';
......@@ -618,7 +620,9 @@ package abb64Package is
constant CINT_BIT_TX_DDR_TOUT_ISR : integer := 6;
constant CINT_BIT_TX_WB_TOUT_ISR : integer := 7;
-- The Time-out bits in System Error Register (SER)
-- Bits in System Error Register (SER)
constant CINT_BIT_DDR_S2MM_SER : integer := 0;
constant CINT_BIT_DDR_MM2S_SER : integer := 1;
constant CINT_BIT_TX_TOUT_IN_SER : integer := 18;
constant CINT_BIT_EB_TOUT_IN_SER : integer := 19;
constant CINT_BIT_EB_OVERWRITTEN : integer := 20;
......@@ -626,6 +630,10 @@ package abb64Package is
-- Bit definition of msg routing method in General Control Register (GCR)
constant C_GCR_MSG_ROUT_BIT_BOT : integer := 0;
constant C_GCR_MSG_ROUT_BIT_TOP : integer := 2;
constant C_GCR_MWR_PAR_BIT_BOT : integer := 8;
constant C_GCR_MWR_PAR_BIT_TOP : integer := 13;
constant C_GCR_DDR_RST_BIT : integer := 16;
constant C_GCR_DDR_AXIRST_BIT : integer := 17;
-- Bit definition of Data Generator available in global status register (GSR)
constant CINT_BIT_DG_AVAIL_IN_GSR : integer := 5;
......@@ -634,8 +642,11 @@ package abb64Package is
constant CINT_BIT_DDR_RDY_GSR : integer := 7;
-- Bit range of link width in GSR
constant CINT_BIT_LWIDTH_IN_GSR_BOT : integer := 10; -- 16;
constant CINT_BIT_LWIDTH_IN_GSR_TOP : integer := 15; -- 21;
constant CINT_BIT_LWIDTH_IN_GSR_BOT : integer := 10;
constant CINT_BIT_LWIDTH_IN_GSR_TOP : integer := 15;
-- Bit range of cfg_dcommand in GSR
constant CINT_BIT_DCOMM_IN_GSR_BOT : integer := 16;
constant CINT_BIT_DCOMM_IN_GSR_TOP : integer := 31;
----------------------------------------------------------------------------------
-- Carry bit, only for better timing, used to divide 32-bit add into 2 stages
......@@ -680,7 +691,7 @@ package abb64Package is
--
function Endian_Invert_32 (Word_in : std_logic_vector) return std_logic_vector;
function Endian_Invert_64 (Word_in : std_logic_vector(64-1 downto 0)) return std_logic_vector;
function Endian_Invert_tkeep (tkeep_in : std_logic_vector) return std_logic_vector;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
......@@ -716,4 +727,19 @@ package body abb64Package is
& Word_in(7 downto 0)&Word_in(15 downto 8)&Word_in(23 downto 16)&Word_in(31 downto 24);
end Endian_Invert_64;
function Endian_Invert_tkeep (tkeep_in : std_logic_vector) return std_logic_vector is
begin
if tkeep_in'length = 4 then
return tkeep_in(0)&tkeep_in(1)&tkeep_in(2)&tkeep_in(3);
elsif tkeep_in'length = 8 then
return tkeep_in(4)&tkeep_in(5)&tkeep_in(6)&tkeep_in(7) &
tkeep_in(0)&tkeep_in(1)&tkeep_in(2)&tkeep_in(3);
else
return tkeep_in;
end if;
assert tkeep_in'length = 4 or tkeep_in'length = 8
report "tkeep length must be 4 or 8"
severity failure;
end Endian_Invert_tkeep;
end abb64Package;
hdl/top/pcie/top_k7.vhd
View file @ 8b84e235
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