top/*/dbe_pbpm: fix outdated CE constraints

These contraints are not correct for PBPM as the CE for this board are 1 for TBT/FOFB and 8 for MONIT/MONIT1.

top/*/dbe_pbpm: fix outdated CE constraints
These contraints are not correct for PBPM as the CE for this board are 1 for TBT/FOFB and 8 for MONIT/MONIT1.
9101fb05 · Lucas Russo · 2a1d4d10 · 9101fb05
Commit 9101fb05 authored Mar 20, 2017 by Lucas Russo
Hide whitespace changes
Inline Side-by-side

Showing with 4 additions and 4 deletions

dbe_pbpm.xdc hdl/top/afc_v3/vivado/dbe_pbpm/dbe_pbpm.xdc +4 -4

No files found.
--- a/hdl/top/afc_v3/vivado/dbe_pbpm/dbe_pbpm.xdc
+++ b/hdl/top/afc_v3/vivado/dbe_pbpm/dbe_pbpm.xdc
@@ -489,8 +489,8 @@ resize_pblock [get_pblocks GRP_pcie_core] -add {CLOCKREGION_X0Y4:CLOCKREGION_X0Y
 #set_multicycle_path 1 -hold -from  [all_fanout -endpoints_only -only_cells -from [get_pins * -hierarchical -filter {NAME =~ *position_calc/gen_ddc[?].cmp_tbt_cic/cmp_cic_decim*/*}]]

 ## TBT CORDIC CE
-set_multicycle_path 4 -setup -from [all_fanout -endpoints_only -only_cells -from [get_pins * -hierarchical -filter {NAME =~ *position_calc/gen_ddc[?].cmp_tbt_cordic/cmp_cordic_core/*}]]
-set_multicycle_path 3 -hold -from [all_fanout -endpoints_only -only_cells -from [get_pins * -hierarchical -filter {NAME =~ *position_calc/gen_ddc[?].cmp_tbt_cordic/cmp_cordic_core/*}]]
+#set_multicycle_path 4 -setup -from [all_fanout -endpoints_only -only_cells -from [get_pins * -hierarchical -filter {NAME =~ *position_calc/gen_ddc[?].cmp_tbt_cordic/cmp_cordic_core/*}]]
+#set_multicycle_path 3 -hold -from [all_fanout -endpoints_only -only_cells -from [get_pins * -hierarchical -filter {NAME =~ *position_calc/gen_ddc[?].cmp_tbt_cordic/cmp_cordic_core/*}]]

 ## CIC FOFB CE
 #set_multicycle_path 2 -setup -from [all_fanout -endpoints_only -only_cells -from [get_pins * -hierarchical -filter {NAME =~ *position_calc/gen_ddc[?].cmp_fofb_cic/cmp_cic_decim*/*}]]
@@ -498,8 +498,8 @@ set_multicycle_path 3 -hold -from [all_fanout -endpoints_only -only_cells -from

 ## FOFB CORDIC CE
 # FIXME: get CE from VHDL code
-set_multicycle_path 4 -setup -from [all_fanout -endpoints_only -only_cells -from [get_pins * -hierarchical -filter {NAME =~ *position_calc/gen_ddc[?].cmp_fofb_cordic/cmp_cordic_core/*}]]
-set_multicycle_path 3 -hold -from [all_fanout -endpoints_only -only_cells -from [get_pins * -hierarchical -filter {NAME =~ *position_calc/gen_ddc[?].cmp_fofb_cordic/cmp_cordic_core/*}]]
+#set_multicycle_path 4 -setup -from [all_fanout -endpoints_only -only_cells -from [get_pins * -hierarchical -filter {NAME =~ *position_calc/gen_ddc[?].cmp_fofb_cordic/cmp_cordic_core/*}]]
+#set_multicycle_path 3 -hold -from [all_fanout -endpoints_only -only_cells -from [get_pins * -hierarchical -filter {NAME =~ *position_calc/gen_ddc[?].cmp_fofb_cordic/cmp_cordic_core/*}]]

 ## CIC MONIT 1 CE
 set_multicycle_path 8 -setup -from [all_fanout -endpoints_only -only_cells -from [get_pins * -hierarchical -filter {NAME =~ *position_calc/gen_ddc[?].cmp_monit1_cic/cmp_cic_decim/*}]]