hdl/modules/pcie/*: add DDR3 debug signals

These signal let us tap directly into the ddr3 memory controller signals

hdl/modules/pcie/*: add DDR3 debug signals
These signal let us tap directly into the ddr3 memory controller signals
93f0d3ea · Lucas Russo · a98a28c1 · 93f0d3ea · 93f0d3ea · 93f0d3ea
Commit 93f0d3ea authored Dec 12, 2013 by Lucas Russo
4 changed files
--- a/hdl/modules/pcie/bpm_pcie_ml605.vhd
+++ b/hdl/modules/pcie/bpm_pcie_ml605.vhd
@@ -127,7 +127,26 @@ entity bpm_pcie_ml605 is
    CYC_O : out std_logic;
    --/ Wishbone interface
    -- Additional exported signals for instantiation
-    ext_rst_o : out std_logic
+    ext_rst_o : out std_logic;
+    -- Debug signals
+    dbg_app_addr_o           : out   std_logic_vector(31 downto 0);
+    dbg_app_cmd_o            : out   std_logic_vector(2 downto 0); 
+    dbg_app_en_o             : out   std_logic; 
+    dbg_app_wdf_data_o       : out   std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0); 
+    dbg_app_wdf_end_o        : out   std_logic;
+    dbg_app_wdf_wren_o       : out   std_logic;
+    dbg_app_wdf_mask_o       : out   std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
+    dbg_app_rd_data_o        : out   std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
+    dbg_app_rd_data_end_o    : out   std_logic;
+    dbg_app_rd_data_valid_o  : out   std_logic;
+    dbg_app_rdy_o            : out   std_logic;
+    dbg_app_wdf_rdy_o        : out   std_logic;
+    dbg_ddr_ui_clk_o         : out   std_logic;
+    dbg_ddr_ui_reset_o       : out   std_logic;
+    dbg_arb_req_o            : out std_logic_vector(1 downto 0);
+    dbg_arb_gnt_o            : out std_logic_vector(1 downto 0)
    );
 end entity bpm_pcie_ml605;
@@ -435,7 +454,10 @@ architecture Behavioral of bpm_pcie_ml605 is
      --clocking & reset
      user_clk      : in std_logic;
-      user_reset    : in std_logic
+      user_reset    : in std_logic;
+      dbg_arb_req_o : out std_logic_vector(1 downto 0);
+      dbg_arb_gnt_o : out std_logic_vector(1 downto 0)
      );
  end component;
@@ -1136,7 +1158,11 @@ begin
        --clocking & reset
        user_clk      => user_clk , --  IN    std_logic;
-        user_reset    => user_reset --  IN    std_logic
+        user_reset    => user_reset, --  IN    std_logic
+        dbg_arb_req_o => dbg_arb_req_o,
+        dbg_arb_gnt_o => dbg_arb_gnt_o
        );
  end generate;
@@ -1284,6 +1310,20 @@ begin
  ddr_ref_clk_i   <= ddr_sys_clk_p;
  ddr_sys_reset_i <= ddr_core_rst;
  memc_ui_rst     <= ddr_ui_reset;
+  dbg_app_addr_o           <= "0000" & app_addr;
+  dbg_app_cmd_o            <= app_cmd;
+  dbg_app_en_o             <= app_en;
+  dbg_app_wdf_data_o       <= app_wdf_data;
+  dbg_app_wdf_end_o        <= app_wdf_end;
+  dbg_app_wdf_wren_o       <= app_wdf_wren;
+  dbg_app_wdf_mask_o       <= app_wdf_mask;
+  dbg_app_rd_data_o        <= app_rd_data;
+  dbg_app_rd_data_end_o    <= app_rd_data_end;
+  dbg_app_rd_data_valid_o  <= app_rd_data_valid;
+  dbg_app_rdy_o            <= app_rdy;
+  dbg_app_wdf_rdy_o        <= app_wdf_rdy;
+  dbg_ddr_ui_clk_o         <= ddr_ui_clk;
+  dbg_ddr_ui_reset_o       <= ddr_ui_reset;
 end Behavioral;
--- a/hdl/modules/pcie/bpm_pcie_pkg.vhd
+++ b/hdl/modules/pcie/bpm_pcie_pkg.vhd
@@ -101,7 +101,26 @@ package bpm_pcie_pkg is
    CYC_O : out std_logic;
    --/ Wishbone interface
    -- Additional exported signals for instantiation
-    ext_rst_o : out std_logic
+    ext_rst_o : out std_logic;
+    -- Debug signals
+    dbg_app_addr_o           : out   std_logic_vector(31 downto 0);
+    dbg_app_cmd_o            : out   std_logic_vector(2 downto 0); 
+    dbg_app_en_o             : out   std_logic; 
+    dbg_app_wdf_data_o       : out   std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0); 
+    dbg_app_wdf_end_o        : out   std_logic;
+    dbg_app_wdf_wren_o       : out   std_logic;
+    dbg_app_wdf_mask_o       : out   std_logic_vector(DDR_PAYLOAD_WIDTH/8-1 downto 0);
+    dbg_app_rd_data_o        : out   std_logic_vector(DDR_PAYLOAD_WIDTH-1 downto 0);
+    dbg_app_rd_data_end_o    : out   std_logic;
+    dbg_app_rd_data_valid_o  : out   std_logic;
+    dbg_app_rdy_o            : out   std_logic;
+    dbg_app_wdf_rdy_o        : out   std_logic;
+    dbg_ddr_ui_clk_o         : out   std_logic;
+    dbg_ddr_ui_reset_o       : out   std_logic;
+    dbg_arb_req_o            : out std_logic_vector(1 downto 0);
+    dbg_arb_gnt_o            : out std_logic_vector(1 downto 0)
    );
  end component;

--- a/hdl/modules/pcie/common/Manifest.py
+++ b/hdl/modules/pcie/common/Manifest.py
@@ -20,4 +20,5 @@ files = ["v6abb64Package_efifo_elink.vhd",
         "tx_Mem_Reader.vhd",
         "tx_Transact.vhd",
         "wb_transact.vhd",
-         "wb_mem.vhd"]
+         "wb_mem.vhd",
+         "sfifo_15x128_tim.vhd"]
--- a/hdl/modules/pcie/common/ddr_Transact.vhd
+++ b/hdl/modules/pcie/common/ddr_Transact.vhd
@@ -100,7 +100,10 @@ entity DDR_Transact is
    --clocking & reset
    user_clk      : in std_logic;
-    user_reset    : in std_logic
+    user_reset    : in std_logic;
+    dbg_arb_req_o : out std_logic_vector(1 downto 0);
+    dbg_arb_gnt_o : out std_logic_vector(1 downto 0)
    );
 end entity DDR_Transact;
@@ -308,8 +311,8 @@ begin
  end process;
  arb_req <= ext_arb_req & pcie_arb_req;
-  --dbg_arb_req_o <= arb_req;
+  dbg_arb_req_o <= arb_req;
-  --dbg_arb_gnt_o <= ext_arb_gnt & pcie_arb_gnt; -- for debug
+  dbg_arb_gnt_o <= ext_arb_gnt & pcie_arb_gnt; -- for debug
  ddr_core_arb_mux :
  process (ddr_switch0, ddr_switch1, ddr_switch2, ddr_switch3, ddr_switch4, pcie_cmd_addr, pcie_cmd_instr, pcie_cmd_en, pcie_wr_data, pcie_wr_en, pcie_wr_end, pcie_wr_mask,