hdl/modules/*/wb_acq_core/*: Rework output data aggregation

This commit introduces a relatively big change in the way
we make tranfers to external memory.

Prior to this, the acq_ddr3_iface module aggregated the
received data (usually 64 or 128 bits) into a DDR3 UI data
packet (usually 256 or 512 bits) in the DDR3 clock domain.
This worked fine, as the DDR3 clock was 200 MHz for Virtex6
(working in 2:1 PHY clock ratio) and the maximum input date
rate was 117 MHz.

But, for Artix7, the DDR3 clock is 100 MHz (working in 4:1 PHY
clock ratio) and the maximum input data rate is still 117 MHz.
This forced the async FIFO to become full and to drop valid data.

However, the UI data width is still 256 or 512 bits and the incoming
data is 64 or 128 bits. This allows us to use two, for or even
eight data buffers (in the incoming clock domain) to aggregate
the whole 256 or 512 bits (which should happen at minimum of 2
clock cycles and can take up to 8 clock cycles) and only then
send it to the DDR3 clock domain.

Now, the data aggregatrion was moved to the incoming clock domain,
in acq_fc_fifo and the acq_ddr3_iface module was simplified, as it
only has to generate the DDR3 addresses and drive the UI lines.

This fixes #37 github issue.