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Beam Positoning Monitor - Gateware
Commit 9bd88252 authored by Lucas Russo's avatar Lucas Russo
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Merge branch 'wb-fmc516-devel' into dsp-devel 

Conflicts:
	embedded-sw/dbe.vhd
parents b94f2bdb 689dbf4a
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embedded-sw/dbe.vhd
View file @ 9bd88252
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embedded-sw/fmc/fmc516/fmc516.c
View file @ 9bd88252
......@@ -94,24 +94,24 @@ void fmc516_sweep_delays(unsigned int id)
int commit = 1;
int i, j;
dbg_print("> ADC%d data delay: %d...\n", 0, FMC516_CH0_CTL_DATA_CHAIN_DLY_R(fmc516[id]->CH0_CTL));
dbg_print("> ADC%d data delay: %d...\n", 1, FMC516_CH1_CTL_DATA_CHAIN_DLY_R(fmc516[id]->CH1_CTL));
dbg_print("> ADC%d data delay: %d...\n", 2, FMC516_CH2_CTL_DATA_CHAIN_DLY_R(fmc516[id]->CH2_CTL));
dbg_print("> ADC%d data delay: %d...\n", 3, FMC516_CH3_CTL_DATA_CHAIN_DLY_R(fmc516[id]->CH3_CTL));
dbg_print("> ADC%d data delay: %d...\n", 0, FMC516_CH0_FN_DLY_DATA_CHAIN_DLY_R(fmc516[id]->CH0_FN_DLY));
dbg_print("> ADC%d data delay: %d...\n", 1, FMC516_CH1_FN_DLY_DATA_CHAIN_DLY_R(fmc516[id]->CH1_FN_DLY));
dbg_print("> ADC%d data delay: %d...\n", 2, FMC516_CH2_FN_DLY_DATA_CHAIN_DLY_R(fmc516[id]->CH2_FN_DLY));
dbg_print("> ADC%d data delay: %d...\n", 3, FMC516_CH3_FN_DLY_DATA_CHAIN_DLY_R(fmc516[id]->CH3_FN_DLY));
//for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
//for (j = 0; j < 32; ++j) {
// dbg_print("> sweeping ADC%d clk delay values: %d...\n", 1, j);
// fmc516_adj_delay(id, FMC516_ISLA216_ADC1, -1, j, commit);
// delay(80000000);
// dbg_print("> ADC%d data delay: %d...\n", 0, FMC516_CH0_CTL_CLK_CHAIN_DLY_R(fmc516[id]->CH0_CTL));
// dbg_print("> ADC%d data delay: %d...\n", 0, FMC516_CH0_CTL_CLK_CHAIN_DLY_R(fmc516[id]->CH0_FN_DLY));
//}
//for (j = 0; j < 32; ++j) {
// dbg_print("> sweeping ADC%d clk delay values: %d...\n", 2, j);
// fmc516_adj_delay(id, FMC516_ISLA216_ADC2, -1, j, commit);
// delay(150000000);
// dbg_print("> ADC%d data delay: %d...\n", 2, FMC516_CH2_CTL_CLK_CHAIN_DLY_R(fmc516[id]->CH2_CTL));
// dbg_print("> ADC%d data delay: %d...\n", 2, FMC516_CH2_CTL_CLK_CHAIN_DLY_R(fmc516[id]->CH2_FN_DLY));
//}
//}
}
......@@ -134,20 +134,20 @@ void fmc516_adj_delay(unsigned int id, int ch, int clk_dly, int data_dly, int co
// Find the correct ADC instance to operate on
switch(ch) {
case FMC516_ISLA216_ADC0:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_FN_DLY;
break;
case FMC516_ISLA216_ADC1:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH1_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH1_FN_DLY;
break;
case FMC516_ISLA216_ADC2:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH2_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH2_FN_DLY;
break;
case FMC516_ISLA216_ADC3:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH3_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH3_FN_DLY;
break;
default:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_FN_DLY;
}
// Read the register value once
......@@ -157,15 +157,15 @@ void fmc516_adj_delay(unsigned int id, int ch, int clk_dly, int data_dly, int co
/* All Read/Write macros are the same for all channels. Use the first one */
if (clk_dly != -1) {
/* Clear clk delay bits and write the desired value*/
adc_ctl_reg = (adc_ctl_reg & ~FMC516_CH0_CTL_CLK_CHAIN_DLY_MASK) |
FMC516_CH0_CTL_CLK_CHAIN_DLY_W(clk_dly);
adc_ctl_reg = (adc_ctl_reg & ~FMC516_CH0_FN_DLY_CLK_CHAIN_DLY_MASK) |
FMC516_CH0_FN_DLY_CLK_CHAIN_DLY_W(clk_dly);
}
if (data_dly != -1) {
/* Clear clk delay bits and write the desired value*/
adc_ctl_reg = (adc_ctl_reg & ~FMC516_CH0_CTL_DATA_CHAIN_DLY_MASK) |
FMC516_CH0_CTL_DATA_CHAIN_DLY_W(data_dly);
adc_ctl_reg = (adc_ctl_reg & ~FMC516_CH0_FN_DLY_DATA_CHAIN_DLY_MASK) |
FMC516_CH0_FN_DLY_DATA_CHAIN_DLY_W(data_dly);
}
......@@ -240,38 +240,44 @@ void fmc516_fe_rg_dly(unsigned int id, int ch, int fe_dly_d1, int fe_dly_d2,
switch(ch) {
case FMC516_ISLA216_ADC0:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_DLY_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_CS_DLY;
break;
case FMC516_ISLA216_ADC1:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH1_DLY_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH1_CS_DLY;
break;
case FMC516_ISLA216_ADC2:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH2_DLY_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH2_CS_DLY;
break;
case FMC516_ISLA216_ADC3:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH3_DLY_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH3_CS_DLY;
break;
default:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_DLY_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_CS_DLY;
}
// Read register value once
dly_ctl_reg = *fmc_ch_handler;
if (fe_dly_d2)
dly_ctl_reg |= (dly_ctl_reg & ~FMC516_CH0_DLY_CTL_FE_DLY_MASK) |
FMC516_CH0_DLY_CTL_FE_DLY_W(0x3);
dly_ctl_reg = (dly_ctl_reg & ~FMC516_CH0_CS_DLY_FE_DLY_MASK) |
FMC516_CH0_CS_DLY_FE_DLY_W(0x3);
else if (fe_dly_d1)
dly_ctl_reg |= (dly_ctl_reg & ~FMC516_CH0_DLY_CTL_FE_DLY_MASK) |
FMC516_CH0_DLY_CTL_FE_DLY_W(0x1);
dly_ctl_reg = (dly_ctl_reg & ~FMC516_CH0_CS_DLY_FE_DLY_MASK) |
FMC516_CH0_CS_DLY_FE_DLY_W(0x1);
else
dly_ctl_reg = (dly_ctl_reg & ~FMC516_CH0_CS_DLY_FE_DLY_MASK) |
FMC516_CH0_CS_DLY_FE_DLY_W(0x0);
if (rg_dly_d2)
dly_ctl_reg |= (dly_ctl_reg & ~FMC516_CH0_DLY_CTL_RG_DLY_MASK) |
FMC516_CH0_DLY_CTL_RG_DLY_W(0x3);
dly_ctl_reg = (dly_ctl_reg & ~FMC516_CH0_CS_DLY_RG_DLY_MASK) |
FMC516_CH0_CS_DLY_RG_DLY_W(0x3);
else if (rg_dly_d1)
dly_ctl_reg |= (dly_ctl_reg & ~FMC516_CH0_DLY_CTL_RG_DLY_MASK) |
FMC516_CH0_DLY_CTL_RG_DLY_W(0x1);
dly_ctl_reg = (dly_ctl_reg & ~FMC516_CH0_CS_DLY_RG_DLY_MASK) |
FMC516_CH0_CS_DLY_RG_DLY_W(0x1);
else
dly_ctl_reg = (dly_ctl_reg & ~FMC516_CH0_CS_DLY_RG_DLY_MASK) |
FMC516_CH0_CS_DLY_RG_DLY_W(0x0);
// Write register value once
*fmc_ch_handler = dly_ctl_reg;
......
embedded-sw/include/hw/wb_fmc516.h
View file @ 9bd88252
This diff is collapsed.
hdl/modules/custom_wishbone/custom_wishbone_pkg.vhd
View file @ 9bd88252
......@@ -481,11 +481,11 @@ package custom_wishbone_pkg is
wbs_err_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
wbs_rty_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
adc_dly_reg_debug_o : out t_adc_dly_reg_array(c_num_adc_channels-1 downto 0);
adc_dly_debug_o : out t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
fifo_debug_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_full_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_empty_o : out std_logic_vector(c_num_adc_channels-1 downto 0)
fifo_debug_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_full_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_empty_o : out std_logic_vector(c_num_adc_channels-1 downto 0)
);
end component;
......@@ -626,7 +626,7 @@ package custom_wishbone_pkg is
wbs_source_i : in t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
wbs_source_o : out t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
adc_dly_reg_debug_o : out t_adc_dly_reg_array(c_num_adc_channels-1 downto 0);
adc_dly_debug_o : out t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
fifo_debug_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_full_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
......
hdl/modules/custom_wishbone/wb_fmc516/Manifest.py
View file @ 9bd88252
modules = { "local" : ["coregen"] };
#modules = { "local" : ["coregen"] };
files = [ "wb_fmc516.vhd", "xwb_fmc516.vhd", "fmc516_adc_clk.vhd",
files = [ "wb_fmc516.vhd", "xwb_fmc516.vhd", "fmc516_adc_clk.vhd",
"fmc516_adc_data.vhd", "fmc516_adc_buf.vhd", "fmc516_adc_iface.vhd",
"wbgen/wb_fmc516_regs_pkg.vhd", "wbgen/wb_fmc516_regs.vhd",
"fmc516_pkg.vhd"
......
hdl/modules/custom_wishbone/wb_fmc516/coregen/Manifest.py deleted 100644 → 0
View file @ b94f2bdb
# Select between synthesis or simulation components
if (action == "synthesis" ):
if(target == "xilinx" and syn_device[0:4].upper()=="XC6V"):
files = ["cdc_fifo.ngc", "adc_data_cdc_fifo.ngc", "cdc_fifo.vhd", "adc_data_cdc_fifo.vhd"];
else:
print "WARNING: Device not supported for synthesis using the FMC516 core!"
elif (action == "simulation"):
if (target == "xilinx"):
files = ["cdc_fifo.vhd", "adc_data_cdc_fifo.vhd"];
else:
print "WARNING: Device not supported for simulation using the FMC516 core!"
hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_clk.vhd
View file @ 9bd88252
......@@ -103,6 +103,8 @@ architecture rtl of fmc516_adc_clk is
signal adc_clk2x_mmcm_out : std_logic;
signal mmcm_adc_locked_int : std_logic;
-- Clock delay signals
signal adc_clk_dly_val_int : std_logic_vector(4 downto 0);
begin
-----------------------------
......@@ -130,33 +132,60 @@ begin
--
-- HIGH_PERFORMANCE_MODE = TRUE reduces the output
-- jitter in exchange of increase power dissipation
cmp_ibufds_clk_iodelay : iodelaye1
generic map(
IDELAY_TYPE => g_delay_type,
IDELAY_VALUE => g_default_adc_clk_delay,
SIGNAL_PATTERN => "CLOCK",
HIGH_PERFORMANCE_MODE => TRUE,
DELAY_SRC => "I"
)
port map(
--idatain => adc_clk_ibufgds,
idatain => adc_clk_i,
dataout => adc_clk_ibufgds_dly,
c => sys_clk_i,
--c => sys_clk_200Mhz_i,
--c => adc_clk_bufg,
--ce => adc_clk_dly_pulse_i,
ce => '0',
inc => adc_clk_dly_incdec_i,
datain => '0',
odatain => '0',
clkin => '0',
rst => adc_clk_dly_pulse_i,
cntvaluein => adc_clk_dly_val_i,
cntvalueout => adc_clk_dly_val_o,
cinvctrl => '0',
t => '1'
);
gen_adc_clk_var_loadable_iodelay : if g_delay_type = "VAR_LOADABLE" generate
cmp_ibufds_clk_iodelay : iodelaye1
generic map(
IDELAY_TYPE => g_delay_type,
IDELAY_VALUE => g_default_adc_clk_delay,
SIGNAL_PATTERN => "CLOCK",
HIGH_PERFORMANCE_MODE => TRUE,
DELAY_SRC => "I"
)
port map(
idatain => adc_clk_i,
dataout => adc_clk_ibufgds_dly,
c => sys_clk_i,
ce => '0',
--inc => adc_clk_dly_incdec_i,
inc => '0',
datain => '0',
odatain => '0',
clkin => '0',
rst => adc_clk_dly_pulse_i,
cntvaluein => adc_clk_dly_val_i,
cntvalueout => adc_clk_dly_val_int,
cinvctrl => '0',
t => '1'
);
end generate;
gen_adc_clk_variable_iodelay : if g_delay_type = "VARIABLE" generate
cmp_ibufds_clk_iodelay : iodelaye1
generic map(
IDELAY_TYPE => g_delay_type,
IDELAY_VALUE => g_default_adc_clk_delay,
SIGNAL_PATTERN => "CLOCK",
HIGH_PERFORMANCE_MODE => TRUE,
DELAY_SRC => "I"
)
port map(
idatain => adc_clk_i,
dataout => adc_clk_ibufgds_dly,
c => sys_clk_i,
ce => adc_clk_dly_pulse_i,
inc => adc_clk_dly_incdec_i,
datain => '0',
odatain => '0',
clkin => '0',
rst => '0',
cntvaluein => adc_clk_dly_val_i,
cntvalueout => adc_clk_dly_val_int,
cinvctrl => '0',
t => '1'
);
end generate;
adc_clk_dly_val_o <= adc_clk_dly_val_int;
-- Generate BUFMR and connect directly to BUFIO/BUFR
--
......
hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_data.vhd
View file @ 9bd88252
......@@ -196,10 +196,7 @@ begin
--idatain => adc_data_ddr_ibufds(i),
idatain => adc_data_i(i),
dataout => adc_data_ddr_dly(i),
--c => sys_clk_200Mhz_i,
--c => sys_clk_i,
c => adc_clk_bufg_i,
--ce => adc_data_dly_pulse_i,
c => sys_clk_i,
ce => '0',
inc => '0',
datain => '0',
......@@ -228,9 +225,7 @@ begin
--idatain => adc_data_ddr_ibufds(i),
idatain => adc_data_i(i),
dataout => adc_data_ddr_dly(i),
--c => sys_clk_200Mhz_i,
c => sys_clk_i,
--c => adc_clk_bufg_i,
ce => adc_data_dly_pulse_i,
inc => adc_data_dly_incdec_i,
datain => '0',
......@@ -339,100 +334,26 @@ begin
-- On the other hand, BUFG and BUFR/BUFIO are not guaranteed to be phase-matched,
-- as they drive independently clock nets. Hence, a FIFO is needed to employ
-- a clock domain crossing.
gen_generic_bufr_bufg_fifo : if g_sim = 0 generate
-- Xilinx coregen async 250 MHz fifo, 512 depth, 16-bit width,
-- built-in fifo primitive, stardard fifo (no fall through)
--cmp_adc_data_async_fifo : cdc_fifo
--port map (
-- rst => sys_rst,
--
-- -- write port
-- wr_clk => adc_clk_bufr_i,
-- din => adc_data_ff_d2,
-- wr_en => adc_fifo_wr,
-- full => adc_fifo_full,
--
-- -- read port
-- rd_clk => adc_clk_bufg_i,
-- dout => adc_data_bufg_sync,
-- rd_en => adc_fifo_rd,
-- valid => adc_fifo_valid,
-- empty => adc_fifo_empty
--);
-- Xilinx coregen async 250 MHz fifo, 16 depth, 16-bit width,
-- distributed ram primitive, stardard fifo (no fall through),
-- cycle accurate simulation model
--cmp_adc_data_async_fifo : adc_data_cdc_fifo
--port map (
-- rst => sys_rst,
--
-- -- write port
-- wr_clk => adc_clk_bufr_i,
-- din => adc_data_ff_d2,
-- wr_en => adc_fifo_wr,
-- full => adc_fifo_full,
--
-- -- read port
-- rd_clk => adc_clk_bufg_i,
-- dout => adc_data_bufg_sync,
-- rd_en => adc_fifo_rd,
-- valid => adc_fifo_valid,
-- empty => adc_fifo_empty
--);
--
--adc_data_valid_out <= adc_fifo_valid;
cmp_adc_data_async_fifo : generic_async_fifo
generic map(
g_data_width => c_num_adc_bits,
g_size => async_fifo_size
)
port map(
rst_n_i => sys_rst_n_i,
-- write port
clk_wr_i => adc_clk_bufr_i,
d_i => adc_data_ff_d2,
we_i => adc_fifo_wr,
wr_full_o => adc_fifo_full,
-- read port
clk_rd_i => adc_clk_bufg_i,
q_o => adc_data_bufg_sync,
rd_i => adc_fifo_rd,
rd_empty_o => adc_fifo_empty
);
end generate;
-- Instanciate a inferred async fifo as the xilinx primitives
-- are not cycle accurate in behavioural simulation for ISim
gen_inferred_bufr_bufg_fifo : if g_sim = 1 generate
cmp_inferred_async_fifo : inferred_async_fifo
generic map (
g_data_width => c_num_adc_bits,
g_size => async_fifo_size,
g_almost_empty_threshold => 3,
g_almost_full_threshold => async_fifo_size-3
)
port map(
rst_n_i => sys_rst_n_i,
-- write port
clk_wr_i => adc_clk_bufr_i,
d_i => adc_data_ff_d2,
we_i => adc_fifo_wr,
wr_full_o => adc_fifo_full,
-- read port
clk_rd_i => adc_clk_bufg_i,
q_o => adc_data_bufg_sync,
rd_i => adc_fifo_rd,
rd_empty_o => adc_fifo_empty
);
end generate;
cmp_adc_data_async_fifo : generic_async_fifo
generic map(
g_data_width => c_num_adc_bits,
g_size => async_fifo_size
)
port map(
rst_n_i => sys_rst_n_i,
-- write port
clk_wr_i => adc_clk_bufr_i,
d_i => adc_data_ff_d2,
we_i => adc_fifo_wr,
wr_full_o => adc_fifo_full,
-- read port
clk_rd_i => adc_clk_bufg_i,
q_o => adc_data_bufg_sync,
rd_i => adc_fifo_rd,
rd_empty_o => adc_fifo_empty
);
--Generate valid signal for adc_data_o.
--Just delay the valid adc_fifo_rd signal as the fifo takes
......@@ -441,10 +362,10 @@ begin
p_gen_valid : process (adc_clk_bufg_i)
begin
if rising_edge (adc_clk_bufg_i) then
if sys_rst_n_i = '0' then
adc_data_valid_out <= adc_fifo_rd;
if adc_fifo_empty = '1' then
adc_data_valid_out <= '0';
else
adc_data_valid_out <= adc_fifo_rd;
end if;
end if;
end process;
......
hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_iface.vhd
View file @ 9bd88252
......@@ -81,12 +81,12 @@ port
-----------------------------
-- ADC Delay signals.
-----------------------------
-- ADC clock + data delays
adc_dly_i : in t_adc_dly_array(c_num_adc_channels-1 downto 0);
adc_dly_o : out t_adc_dly_array(c_num_adc_channels-1 downto 0);
-- ADC fine delay control
adc_fn_dly_i : in t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
adc_fn_dly_o : out t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
-- ADC falling edge delay control
adc_dly_ctl_i : in t_adc_dly_ctl_array(c_num_adc_channels-1 downto 0);
-- ADC coarse delay control (falling edge + regular delay)
adc_cs_dly_i : in t_adc_cs_dly_array(c_num_adc_channels-1 downto 0);
-----------------------------
-- ADC output signals.
......@@ -135,13 +135,16 @@ architecture rtl of fmc516_adc_iface is
type t_adc_clk_chain_array is array (natural range <>) of t_adc_clk_chain;
--type t_adc_data_chain_array is array (natural range <>) of t_adc_data_chain;
-- Conectivity vector for interconnecting clocks and data chains
--type t_chain_intercon is array (natural range <>) of integer;
-- ADC and Clock chains
signal adc_clk_chain : t_adc_clk_chain_array(c_num_adc_channels-1 downto 0);
signal adc_data_chain_out : t_adc_int_array(c_num_adc_channels-1 downto 0);
type t_adc_fn_dly_val_array is array (natural range <>) of std_logic_vector(4 downto 0);
-- ADC fine delay internal signal
signal adc_fn_clk_dly_int_out : t_adc_fn_dly_val_array(c_num_adc_channels-1 downto 0);
signal adc_fn_data_dly_int_out : t_adc_fn_dly_val_array(c_num_adc_channels-1 downto 0);
-----------------------------
-- Components declaration
-----------------------------
......@@ -166,7 +169,7 @@ architecture rtl of fmc516_adc_iface is
-----------------------------
-- ADC clocks. One clock per ADC channel
adc_clk_i : in std_logic;
adc_clk_i : in std_logic;
-----------------------------
-- ADC Delay signals.
......@@ -230,7 +233,7 @@ architecture rtl of fmc516_adc_iface is
adc_data_dly_val_i : in std_logic_vector(4 downto 0);
adc_data_dly_val_o : out std_logic_vector(4 downto 0);
-- idelay variable interface
-- idelay variable interface
adc_data_dly_incdec_i : in std_logic;
-- Pulse this to update the delay value or reset to its default (depending
......@@ -298,10 +301,10 @@ begin
-- ADC Delay signals.
-----------------------------
-- Pulse this to update the delay value
adc_clk_dly_pulse_i => adc_dly_i(i).adc_clk_dly_pulse,
adc_clk_dly_val_i => adc_dly_i(i).adc_clk_dly_val,
adc_clk_dly_val_o => adc_dly_o(i).adc_clk_dly_val,
adc_clk_dly_incdec_i => adc_dly_i(i).adc_clk_dly_incdec,
adc_clk_dly_pulse_i => adc_fn_dly_i(i).adc_clk_dly_pulse,
adc_clk_dly_val_i => adc_fn_dly_i(i).adc_clk_dly_val,
adc_clk_dly_val_o => adc_fn_clk_dly_int_out(i),
adc_clk_dly_incdec_i => adc_fn_dly_i(i).adc_clk_dly_incdec,
-----------------------------
-- ADC output signals.
......@@ -379,26 +382,23 @@ begin
-- ADC Data Delay signals.
-----------------------------
-- Pulse this to update the delay value
adc_data_dly_pulse_i => adc_dly_i(i).adc_data_dly_pulse,
adc_data_dly_val_i => adc_dly_i(i).adc_data_dly_val,
adc_data_dly_val_o => adc_dly_o(i).adc_data_dly_val,
adc_data_dly_incdec_i => adc_dly_i(i).adc_data_dly_incdec,
adc_data_dly_pulse_i => adc_fn_dly_i(i).adc_data_dly_pulse,
adc_data_dly_val_i => adc_fn_dly_i(i).adc_data_dly_val,
--adc_data_dly_val_o => adc_fn_dly_o(i).adc_data_dly_val,
adc_data_dly_val_o => adc_fn_data_dly_int_out(i),
adc_data_dly_incdec_i => adc_fn_dly_i(i).adc_data_dly_incdec,
-- Falling edge delay control
adc_data_fe_d1_en_i => adc_dly_ctl_i(i).adc_data_fe_d1_en,
adc_data_fe_d2_en_i => adc_dly_ctl_i(i).adc_data_fe_d2_en,
adc_data_fe_d1_en_i => adc_cs_dly_i(i).adc_data_fe_d1_en,
adc_data_fe_d2_en_i => adc_cs_dly_i(i).adc_data_fe_d2_en,
-- Regular delay control
adc_data_rg_d1_en_i => adc_dly_ctl_i(i).adc_data_rg_d1_en,
adc_data_rg_d2_en_i => adc_dly_ctl_i(i).adc_data_rg_d2_en,
adc_data_rg_d1_en_i => adc_cs_dly_i(i).adc_data_rg_d1_en,
adc_data_rg_d2_en_i => adc_cs_dly_i(i).adc_data_rg_d2_en,
-----------------------------
-- ADC output signals.
-----------------------------
--adc_data_o => adc_data_chain_out(i).adc_data,
--adc_data_valid_o => adc_data_chain_out(i).adc_data_valid,
--adc_clk_o => adc_data_chain_out(i).adc_clk,
--adc_clk2x_o => adc_data_chain_out(i).adc_clk2x,
adc_data_o => adc_out_o(i).adc_data,
adc_data_valid_o => adc_out_o(i).adc_data_valid,
adc_clk_o => adc_out_o(i).adc_clk,
......@@ -408,6 +408,11 @@ begin
fifo_debug_empty_o => fifo_debug_empty_o(i)
);
-- The clock delay information for each channel corresponds to the delay
-- in its correspondent clock chain, referenced by chain_intercon(i).
adc_fn_dly_o(i).adc_data_dly_val <= adc_fn_data_dly_int_out(i);
adc_fn_dly_o(i).adc_clk_dly_val <= adc_fn_clk_dly_int_out(chain_intercon(i));
end generate;
end generate;
......
hdl/modules/custom_wishbone/wb_fmc516/fmc516_pkg.vhd
View file @ 9bd88252
......@@ -49,7 +49,7 @@ package fmc516_pkg is
type t_adc_in_array is array (natural range <>) of t_adc_in;
type t_adc_dly is record
type t_adc_fn_dly is record
adc_clk_dly_pulse : std_logic;
adc_clk_dly_val : std_logic_vector(4 downto 0);
adc_clk_dly_incdec : std_logic;
......@@ -58,41 +58,33 @@ package fmc516_pkg is
adc_data_dly_incdec : std_logic;
end record;
type t_adc_dly_array is array (natural range <>) of t_adc_dly;
type t_adc_fn_dly_array is array (natural range <>) of t_adc_fn_dly;
-- Internal structure for generate statements
-- ADC Data/Clock delay registers for generate statements
type t_adc_dly_reg is record
-- registers to signals coming from wishbone register interface
-- ext_load mode
clk_dly_reg : std_logic_vector(4 downto 0);
data_dly_reg : std_logic_vector(4 downto 0);
clk_dly_incdec : std_logic;
data_dly_incdec : std_logic;
-- signals from wishbone register interface
clk_dly : std_logic_vector(4 downto 0);
clk_dly_inc : std_logic;
clk_dly_dec : std_logic;
data_dly : std_logic_vector(4 downto 0);
data_dly_inc : std_logic;
data_dly_dec : std_logic;
clk_load : std_logic;
data_load : std_logic;
type t_adc_fn_dly_int is record
adc_clk_dly : std_logic_vector(4 downto 0);
adc_clk_dly_inc : std_logic;
adc_clk_dly_dec : std_logic;
adc_clk_load : std_logic;
adc_data_dly : std_logic_vector(4 downto 0);
adc_data_dly_inc : std_logic;
adc_data_dly_dec : std_logic;
adc_data_load : std_logic;
end record;
type t_adc_dly_reg_array is array (natural range<>) of t_adc_dly_reg;
type t_adc_fn_dly_int_array is array (natural range<>) of t_adc_fn_dly_int;
-- ADC falling edge and regular delay control (per channel)
type t_adc_dly_ctl is record
-- ADC coarse delay control (falling edge or whole chain)
type t_adc_cs_dly is record
adc_data_rg_d1_en : std_logic;
adc_data_rg_d2_en : std_logic;
adc_data_fe_d1_en : std_logic;
adc_data_fe_d2_en : std_logic;
end record;
type t_adc_dly_ctl_array is array (natural range<>) of t_adc_dly_ctl;
type t_adc_cs_dly_array is array (natural range<>) of t_adc_cs_dly;
type t_adc_out is record
adc_clk : std_logic;
......
hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.wb
View file @ 9bd88252
......@@ -340,8 +340,8 @@ peripheral {
};
reg {
name = "Channel 0 control register";
prefix = "ch0_ctl";
name = "Channel 0 fine delay register";
prefix = "ch0_fn_dly";
-- Registers for VAR_LOADABLE mode iodelay
field {
......@@ -471,8 +471,8 @@ peripheral {
};
reg {
name = "Channel 0 delay control register";
prefix = "ch0_dly_ctl";
name = "Channel 0 coarse delay register";
prefix = "ch0_cs_dly";
field {
name = "Falling edge data delay";
......@@ -551,8 +551,8 @@ peripheral {
reg {
name = "Channel 1 control register";
prefix = "ch1_ctl";
name = "Channel 1 fine delay register";
prefix = "ch1_fn_dly";
-- Registers for VAR_LOADABLE mode iodelay
field {
......@@ -682,8 +682,8 @@ peripheral {
};
reg {
name = "Channel 1 delay control register";
prefix = "ch1_dly_ctl";
name = "Channel 1 coarse delay register";
prefix = "ch1_cs_dly";
field {
name = "Falling edge data delay";
......@@ -761,8 +761,8 @@ peripheral {
};
reg {
name = "Channel 2 control register";
prefix = "ch2_ctl";
name = "Channel 2 fine delay register";
prefix = "ch2_fn_dly";
-- Registers for VAR_LOADABLE mode iodelay
field {
......@@ -892,8 +892,8 @@ peripheral {
};
reg {
name = "Channel 2 delay control register";
prefix = "ch2_dly_ctl";
name = "Channel 2 coarse delay register";
prefix = "ch2_cs_dly";
field {
name = "Falling edge data delay";
......@@ -971,8 +971,8 @@ peripheral {
};
reg {
name = "Channel 3 control register";
prefix = "ch3_ctl";
name = "Channel 3 fine delay register";
prefix = "ch3_fn_dly";
-- Registers for VAR_LOADABLE mode iodelay
field {
......@@ -1102,8 +1102,8 @@ peripheral {
};
reg {
name = "Channel 3 delay control register";
prefix = "ch3_dly_ctl";
name = "Channel 3 coarse delay register";
prefix = "ch3_cs_dly";
field {
name = "Falling edge data delay";
......
hdl/modules/custom_wishbone/wb_fmc516/xwb_fmc516.vhd
View file @ 9bd88252
......@@ -168,7 +168,7 @@ port
wbs_source_i : in t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
wbs_source_o : out t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
adc_dly_reg_debug_o : out t_adc_dly_reg_array(c_num_adc_channels-1 downto 0);
adc_dly_debug_o : out t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
fifo_debug_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_full_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
......@@ -339,7 +339,7 @@ begin
wbs_err_i => wbs_err_int,
wbs_rty_i => wbs_rty_int,
adc_dly_reg_debug_o => adc_dly_reg_debug_o,
adc_dly_debug_o => adc_dly_debug_o,
fifo_debug_valid_o => fifo_debug_valid_o,
fifo_debug_full_o => fifo_debug_full_o,
......
hdl/sim/regs/wb_fmc516_regs.vh
View file @ 9bd88252
This diff is collapsed.
hdl/syn/dbe_bpm_fmc516/dbe_bpm_fmc516.xise
View file @ 9bd88252
This diff is collapsed.
hdl/syn/dbe_bpm_fmc516/make_output
View file @ 9bd88252
This diff is collapsed.
hdl/top/ml_605/dbe_bpm_fmc516/chipscope.cpj
View file @ 9bd88252
This diff is collapsed.
hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf
View file @ 9bd88252
......@@ -209,7 +209,7 @@ TIMEGRP "TNM_ADC_DATA_3" OFFSET = IN -200 ps VALID 1200 ps BEFORE "adc_clk3_p_i"
# Group all IDELAY-related blocks to use a single IDELAYCTRL
INST "*cmp_fmc516_adc_iface/cmp_idelayctrl" IODELAY_GROUP = adc_idelay;
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[?].*.*/gen_adc_data[?].*.cmp_adc_data_iodelay" IODELAY_GROUP = adc_idelay;
INST "*cmp_fmc516_adc_iface/gen_clock_chains[?].*.*/cmp_ibufds_clk_iodelay" IODELAY_GROUP = adc_idelay;
INST "*cmp_fmc516_adc_iface/gen_clock_chains[?].*.*/*.cmp_ibufds_clk_iodelay" IODELAY_GROUP = adc_idelay;
# Overrides default_delay hdl parameter for the VARIABLE mode.
# For Virtex-6: Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps
......@@ -250,10 +250,10 @@ INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[6].*.cmp_adc
INST "*cmp_fmc516_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[7].*.cmp_adc_data_iodelay" IDELAY_VALUE = 25;
# Overrides default_delay hdl parameter
INST "*cmp_fmc516_adc_iface/gen_clock_chains[0].*.*/cmp_ibufds_clk_iodelay" IDELAY_VALUE = 5;
INST "*cmp_fmc516_adc_iface/gen_clock_chains[1].*.*/cmp_ibufds_clk_iodelay" IDELAY_VALUE = 5;
# INST "*cmp_fmc516_adc_iface/gen_clock_chains[2].*.*/cmp_ibufds_clk_iodelay" IDELAY_VALUE = 5;
# INST "*cmp_fmc516_adc_iface/gen_clock_chains[3].*.*/cmp_ibufds_clk_iodelay" IDELAY_VALUE = 5;
INST "*cmp_fmc516_adc_iface/gen_clock_chains[0].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 5;
INST "*cmp_fmc516_adc_iface/gen_clock_chains[1].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 5;
# INST "*cmp_fmc516_adc_iface/gen_clock_chains[2].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 5;
# INST "*cmp_fmc516_adc_iface/gen_clock_chains[3].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 5;
#######################################################################
# Button/LEDs Contraints
......
hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd
View file @ 9bd88252
......@@ -348,7 +348,7 @@ architecture rtl of dbe_bpm_fmc516 is
signal fmc516_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_dly_reg_debug_int : t_adc_dly_reg_array(c_num_adc_channels-1 downto 0);
signal adc_dly_debug_int : t_adc_fn_dly_array(c_num_adc_channels-1 downto 0);
signal sys_spi_clk_int : std_logic;
--signal sys_spi_data_int : std_logic;
......@@ -907,7 +907,7 @@ begin
wbs_source_i => wbs_fmc516_in_array,
wbs_source_o => wbs_fmc516_out_array,
adc_dly_reg_debug_o => adc_dly_reg_debug_int,
adc_dly_debug_o => adc_dly_debug_int,
fifo_debug_valid_o => fmc516_debug_valid_int,
fifo_debug_full_o => fmc516_debug_full_int,
......@@ -1108,10 +1108,10 @@ begin
-- wbs_fmc516_out_array(0).dat;
--TRIG_ILA0_1 <= fmc516_adc_data(15 downto 0) &
-- fmc516_adc_data(47 downto 32);
TRIG_ILA0_1(11 downto 0) <= adc_dly_reg_debug_int(1).clk_load &
adc_dly_reg_debug_int(1).data_load &
adc_dly_reg_debug_int(1).clk_dly_reg &
adc_dly_reg_debug_int(1).data_dly_reg;
TRIG_ILA0_1(11 downto 0) <= adc_dly_debug_int(1).adc_clk_dly_pulse &
adc_dly_debug_int(1).adc_data_dly_pulse &
adc_dly_debug_int(1).adc_clk_dly_val &
adc_dly_debug_int(1).adc_data_dly_val;
TRIG_ILA0_1(31 downto 12) <= (others => '0');
-- FMC516 WBS master output control signals
......
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