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Beam Positoning Monitor - Gateware
Commit 9d79c12f authored by Lucas Russo's avatar Lucas Russo
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top/afc_v3/*: remove dead DDS simulation code

parent 9ff12a3d
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hdl/top/afc_v3/vivado/dbe_bpm/dbe_bpm.vhd
View file @ 9d79c12f
......@@ -1023,10 +1023,6 @@ architecture rtl of dbe_bpm is
--signal TRIG_ILA10_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA10_4 : std_logic_vector(31 downto 0);
---- Chipscope VIO signals
--signal vio_out : std_logic_vector(255 downto 0);
--signal vio_out_dsp_config : std_logic_vector(255 downto 0);
---------------------------
-- Components --
---------------------------
......@@ -1070,23 +1066,6 @@ architecture rtl of dbe_bpm is
);
end component;
component multiplier_16x10_DSP
port (
clk : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(9 downto 0);
p : out std_logic_vector(25 downto 0)
);
end component;
component dds_adc_input
port (
aclk : in std_logic;
m_axis_data_tvalid : out std_logic;
m_axis_data_tdata : out std_logic_vector(31 downto 0)
);
end component;
component chipscope_icon_4_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
......@@ -3099,26 +3078,6 @@ begin
--TRIG_ILA10_3(dsp_fofb_pha_ch2'left downto 0) <= dsp_fofb_pha_ch2;
--TRIG_ILA10_4(dsp_fofb_pha_ch3'left downto 0) <= dsp_fofb_pha_ch3;
---- Controllable gain for test data
--cmp_chipscope_vio_256 : chipscope_vio_256
--port map (
-- CONTROL => CONTROL11,
-- ASYNC_OUT => vio_out
--);
--dds_sine_gain_ch0 <= vio_out(10-1 downto 0);
--dds_sine_gain_ch1 <= vio_out(20-1 downto 10);
--dds_sine_gain_ch2 <= vio_out(30-1 downto 20);
--dds_sine_gain_ch3 <= vio_out(40-1 downto 30);
--adc_synth_data_en <= vio_out(40);
---- Controllable DDS frequency and phase
--cmp_chipscope_vio_256_dsp_config : chipscope_vio_256
--port map (
-- CONTROL => CONTROL12,
-- ASYNC_OUT => vio_out_dsp_config
--);
----------------------------------------------------------------------
-- AFC Diagnostics Chipscope --
----------------------------------------------------------------------
......
hdl/top/afc_v3/vivado/dbe_bpm2/dbe_bpm2.vhd
View file @ 9d79c12f
......@@ -1046,10 +1046,6 @@ architecture rtl of dbe_bpm2 is
--signal TRIG_ILA10_3 : std_logic_vector(31 downto 0);
--signal TRIG_ILA10_4 : std_logic_vector(31 downto 0);
---- Chipscope VIO signals
--signal vio_out : std_logic_vector(255 downto 0);
--signal vio_out_dsp_config : std_logic_vector(255 downto 0);
---------------------------
-- Components --
---------------------------
......@@ -1093,23 +1089,6 @@ architecture rtl of dbe_bpm2 is
);
end component;
component multiplier_16x10_DSP
port (
clk : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(9 downto 0);
p : out std_logic_vector(25 downto 0)
);
end component;
component dds_adc_input
port (
aclk : in std_logic;
m_axis_data_tvalid : out std_logic;
m_axis_data_tdata : out std_logic_vector(31 downto 0)
);
end component;
component chipscope_icon_4_port
port (
CONTROL0 : inout std_logic_vector(35 downto 0);
......@@ -3143,26 +3122,6 @@ begin
--TRIG_ILA10_3(dsp_fofb_pha_ch2'left downto 0) <= dsp_fofb_pha_ch2;
--TRIG_ILA10_4(dsp_fofb_pha_ch3'left downto 0) <= dsp_fofb_pha_ch3;
---- Controllable gain for test data
--cmp_chipscope_vio_256 : chipscope_vio_256
--port map (
-- CONTROL => CONTROL11,
-- ASYNC_OUT => vio_out
--);
--dds_sine_gain_ch0 <= vio_out(10-1 downto 0);
--dds_sine_gain_ch1 <= vio_out(20-1 downto 10);
--dds_sine_gain_ch2 <= vio_out(30-1 downto 20);
--dds_sine_gain_ch3 <= vio_out(40-1 downto 30);
--adc_synth_data_en <= vio_out(40);
---- Controllable DDS frequency and phase
--cmp_chipscope_vio_256_dsp_config : chipscope_vio_256
--port map (
-- CONTROL => CONTROL12,
-- ASYNC_OUT => vio_out_dsp_config
--);
----------------------------------------------------------------------
-- AFC Diagnostics Chipscope --
----------------------------------------------------------------------
......
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