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Beam Positoning Monitor - Gateware
Commit 9dfd560b authored by Vitor Finotti's avatar Vitor Finotti
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Changed constraint files from /syn/ to /top/

parent 808ca91f
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Showing with 8 additions and 6 deletions
hdl/top/afc_v3/vivado/test_trigger/rcv/Manifest.py
View file @ 9dfd560b
...@@ -2,7 +2,8 @@ files = [ "test_trigger_rcv.vhd", ...@@ -2,7 +2,8 @@ files = [ "test_trigger_rcv.vhd",
"sm_counter.vhd", "sm_counter.vhd",
"sm_states_rcv.vhd", "sm_states_rcv.vhd",
"sys_pll.vhd", "sys_pll.vhd",
"clk_gen.vhd"]; "clk_gen.vhd",
"test_trigger_rcv.xcd"];
modules = { "local" : modules = { "local" :
["../../../../.."] ["../../../../.."]
......
hdl/syn/afc_v3/vivado/test_trigger/rcv/test_trigger_rcv.xdc → hdl/top/afc_v3/vivado/test_trigger/rcv/test_trigger_rcv.xdc
View file @ 9dfd560b
...@@ -9,6 +9,8 @@ set_property PACKAGE_PIN AL7 [get_ports sys_clk_n_i] ...@@ -9,6 +9,8 @@ set_property PACKAGE_PIN AL7 [get_ports sys_clk_n_i]
set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n_i] set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n_i]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports sys_clk_n_i] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports sys_clk_n_i]
# Reset synchronization path
set_false_path -through [get_nets cmp_reset/p_0_in[2]]
#Signal #Signal
set_property PACKAGE_PIN AM9 [get_ports {trigger_i[0]}] set_property PACKAGE_PIN AM9 [get_ports {trigger_i[0]}]
...@@ -37,8 +39,8 @@ set_property IOSTANDARD LVCMOS15 [get_ports {trigger_i[7]}] ...@@ -37,8 +39,8 @@ set_property IOSTANDARD LVCMOS15 [get_ports {trigger_i[7]}]
#Direction #Direction
# set_property PACKAGE_PIN AJ10 [get_ports {direction_o[0]}] set_property PACKAGE_PIN AJ10 [get_ports {direction_o[0]}]
# set_property IOSTANDARD LVCMOS15 [get_ports {direction_o[0]}] set_property IOSTANDARD LVCMOS15 [get_ports {direction_o[0]}]
set_property PACKAGE_PIN AK11 [get_ports {direction_o[1]}] set_property PACKAGE_PIN AK11 [get_ports {direction_o[1]}]
set_property IOSTANDARD LVCMOS15 [get_ports {direction_o[1]}] set_property IOSTANDARD LVCMOS15 [get_ports {direction_o[1]}]
......
hdl/top/afc_v3/vivado/test_trigger/transm/Manifest.py
View file @ 9dfd560b
...@@ -2,7 +2,8 @@ files = [ "test_trigger_transm.vhd", ...@@ -2,7 +2,8 @@ files = [ "test_trigger_transm.vhd",
"sm_transm.vhd", "sm_transm.vhd",
"sys_pll.vhd", "sys_pll.vhd",
"clk_gen.vhd", "clk_gen.vhd",
"extend_pulse_dyn.vhd"]; "extend_pulse_dyn.vhd"
"test_trigger_transm.xcd"];
modules = { "local" : modules = { "local" :
["../../../../.."] ["../../../../.."]
......
hdl/syn/afc_v3/vivado/test_trigger/transm/test_trigger_transm.xdc → hdl/top/afc_v3/vivado/test_trigger/transm/test_trigger_transm.xdc
View file @ 9dfd560b
...@@ -37,8 +37,6 @@ set_property IOSTANDARD LVCMOS15 [get_ports {trigger_o[7]}] ...@@ -37,8 +37,6 @@ set_property IOSTANDARD LVCMOS15 [get_ports {trigger_o[7]}]
#Direction #Direction
#set_property PACKAGE_PIN H12 [get_ports {direction_o[0]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {direction_o[0]}]
set_property PACKAGE_PIN AJ10 [get_ports {direction_o[0]}] set_property PACKAGE_PIN AJ10 [get_ports {direction_o[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {direction_o[0]}] set_property IOSTANDARD LVCMOS15 [get_ports {direction_o[0]}]
......
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