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Beam Positoning Monitor - Gateware
Commit 9ecdb26d authored by Lucas Russo's avatar Lucas Russo
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wb_fmc516/*: add degub signals for delays

parent 9b53ce5b
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Showing with 30 additions and 6 deletions
hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_clk.vhd
View file @ 9ecdb26d
......@@ -217,18 +217,22 @@ begin
-- resourses guide page 53, note 2)
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 4,
CLKFBOUT_MULT_F => 12.000,
--DIVCLK_DIVIDE => 4,
DIVCLK_DIVIDE => 1,
--CLKFBOUT_MULT_F => 12.000,
CLKFBOUT_MULT_F => 6.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
-- adc clock
CLKOUT0_DIVIDE_F => 3.000,
--CLKOUT0_DIVIDE_F => 3.000,
CLKOUT0_DIVIDE_F => 6.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
-- 2x adc clock. This should not be 2x. FIX
--CLKOUT1_DIVIDE => 2,
CLKOUT1_DIVIDE => 3,
--CLKOUT1_DIVIDE => 3,
CLKOUT1_DIVIDE => 6,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
......
hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd
View file @ 9ecdb26d
......@@ -197,6 +197,8 @@ port
wbs_err_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
wbs_rty_i : in std_logic_vector(c_num_adc_channels-1 downto 0) := (others => '0');
adc_dly_reg_debug_o : out t_adc_dly_array;
fifo_debug_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_full_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_empty_o : out std_logic_vector(c_num_adc_channels-1 downto 0)
......@@ -894,6 +896,9 @@ begin
end if;
end if;
end process;
-- Debug interface
adc_dly_reg_debug_o(i) <= adc_dly_reg(i);
end generate;
-- Idelay "variable" interface
......
hdl/modules/custom_wishbone/wb_fmc516/xwb_fmc516.vhd
View file @ 9ecdb26d
......@@ -167,6 +167,8 @@ port
wbs_source_i : in t_wbs_source_in16_array(c_num_adc_channels-1 downto 0);
wbs_source_o : out t_wbs_source_out16_array(c_num_adc_channels-1 downto 0);
adc_dly_reg_debug_o : out t_adc_dly_array;
fifo_debug_valid_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_full_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
fifo_debug_empty_o : out std_logic_vector(c_num_adc_channels-1 downto 0)
......@@ -334,7 +336,13 @@ begin
wbs_ack_i => wbs_ack_int,
wbs_stall_i => wbs_stall_int,
wbs_err_i => wbs_err_int,
wbs_rty_i => wbs_rty_int
wbs_rty_i => wbs_rty_int,
adc_dly_reg_debug_o => adc_dly_reg_debug_o,
fifo_debug_valid_o => fifo_debug_valid_o,
fifo_debug_full_o => fifo_debug_full_o,
fifo_debug_empty_o => fifo_debug_empty_o
);
gen_wbs_interfaces : for i in 0 to c_num_adc_channels-1 generate
......
hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd
View file @ 9ecdb26d
......@@ -344,6 +344,8 @@ architecture rtl of dbe_bpm_fmc516 is
signal fmc516_debug_full_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_debug_empty_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_dly_reg_debug_int : t_adc_dly_array;
signal sys_spi_clk_int : std_logic;
--signal sys_spi_data_int : std_logic;
signal sys_spi_dout_int : std_logic;
......@@ -899,6 +901,8 @@ begin
wbs_source_i => wbs_fmc516_in_array,
wbs_source_o => wbs_fmc516_out_array,
adc_dly_reg_debug_o => adc_dly_reg_debug_int,
fifo_debug_valid_o => fmc516_debug_valid_int,
fifo_debug_full_o => fmc516_debug_full_int,
fifo_debug_empty_o => fmc516_debug_empty_int
......@@ -1095,7 +1099,10 @@ begin
-- wbs_fmc516_out_array(0).dat;
--TRIG_ILA0_1 <= fmc516_adc_data(15 downto 0) &
-- fmc516_adc_data(47 downto 32);
TRIG_ILA0_1 <= (others => '0');
TRIG_ILA0_1 <= adc_dly_reg_debug_int(1).clk_load &
adc_dly_reg_debug_int(1).data_load &
adc_dly_reg_debug_int(1).clk_dly_reg &
adc_dly_reg_debug_int(1).data_dly_reg;
-- FMC516 WBS master output control signals
TRIG_ILA0_2(17 downto 0) <= wbs_fmc516_out_array(1).cyc &
......
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