Skip to content

B
Beam Positoning Monitor - Gateware
Commit a41c2b45 authored by Lucas Russo's avatar Lucas Russo
Browse files
Options

hdl/testbench/*/wb_acq_core_test/*: updates to test with DDR core 2.3

parent 7378936f
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 431 additions and 423 deletions
hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/Manifest.py
View file @ a41c2b45
action = "simulation"
target = "xilinx"
syn_device = "xc7a200t"
sim_tool = "modelsim"
top_module = "wb_acq_core_tb.v"
modules = {"local" : [
"../../../../../../modules/dbe_wishbone",
......@@ -14,11 +16,17 @@ modules = {"local" : [
# "../../../../../../platform/virtex6/chipscope",
# "../../../../../../platform/virtex6/ip_cores",
"../../../../../../platform",
"../../../../../../sim",
"../../../../../../sim/ddr_model",
# "../../../../../../ip_cores/pcie/7a200ffg1156/ddr_core_1_8/user_design/"]}
"../../../../../../ip_cores/pcie/7a200ffg1156/ddr_core/user_design/"]}
# "../../../../../../ip_cores/pcie/7a200ffg1156/ddr_core/user_design/"]}
"../../../../../../ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/"]}
files = ["wb_acq_core_tb.v", "ddr_core_wrapper.vhd", "defines.v", "timescale.v",
"clk_rst.v", "../../../../../../../../../../../opt/Xilinx/14.6/ISE_DS/ISE/verilog/src/glbl.v"]
"clk_rst.v", "../../../../../../sim/wishbone_test_master.v",
"../../../../../../../../../../../opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/glbl.v"]
include_dirs = ["../../../../../../sim", "../../../../../../sim/regs", "../../../../../../sim/ddr_model",
"../../../../../../platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog"]
vlog_opt = "+incdir+../../../../../../sim/regs +incdir+../../../../../../sim +incdir+../../../../../../sim/ddr_model +incdir+../../../../../../platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog"
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment