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Beam Positoning Monitor - Gateware
Commits
a6a10c48
Commit
a6a10c48
authored
Nov 27, 2015
by
Gustavo Bruno
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Trigger receiver module, first version.
parent
84b59a54
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5 changed files
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126 additions
and
1 deletion
+126
-1
.gitignore
.gitignore
+1
-0
Manifest.py
hdl/modules/dbe_common/Manifest.py
+2
-1
dbe_common_pkg.vhd
hdl/modules/dbe_common/dbe_common_pkg.vhd
+13
-0
Manifest.py
hdl/modules/dbe_common/trigger_rcv/Manifest.py
+1
-0
trigger_rcv.vhd
hdl/modules/dbe_common/trigger_rcv/trigger_rcv.vhd
+109
-0
No files found.
.gitignore
View file @
a6a10c48
*~
*~
*.swp
*.swp
*.orig
*.orig
hdl/syn/*.runs*
\ No newline at end of file
hdl/modules/dbe_common/Manifest.py
View file @
a6a10c48
modules
=
{
"local"
:
[
"reset_synch"
,
modules
=
{
"local"
:
[
"reset_synch"
,
"pulse2level"
]
};
"pulse2level"
,
"trigger_rcv"
]
};
files
=
[
"dbe_common_pkg.vhd"
];
files
=
[
"dbe_common_pkg.vhd"
];
hdl/modules/dbe_common/dbe_common_pkg.vhd
View file @
a6a10c48
...
@@ -37,4 +37,17 @@ package dbe_common_pkg is
...
@@ -37,4 +37,17 @@ package dbe_common_pkg is
);
);
end
component
;
end
component
;
component
trigger_rcv
generic
(
g_glitch_len_width
:
positive
;
g_pulse_width
:
positive
);
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
len_i
:
in
std_logic_vector
(
g_glitch_len_width
-1
downto
0
);
data_i
:
in
std_logic
;
pulse_o
:
out
std_logic
);
end
component
;
end
dbe_common_pkg
;
end
dbe_common_pkg
;
hdl/modules/dbe_common/trigger_rcv/Manifest.py
0 → 100644
View file @
a6a10c48
files
=
[
"trigger_rcv.vhd"
];
hdl/modules/dbe_common/trigger_rcv/trigger_rcv.vhd
0 → 100644
View file @
a6a10c48
-------------------------------------------------------------------------------
-- Title : Trigger receiver
-- Project :
-------------------------------------------------------------------------------
-- File : trigger_rcv.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-11-09
-- Last update: 2015-11-10
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Receives a signal from an FPGA port, debounces the signal and
-- outputs a pulse with a configurable clock width.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-11-09 1.0 aylons Created
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
gencores_pkg
.
all
;
entity
trigger_rcv
is
generic
(
-- Number of glicth filter registers
g_glitch_len_width
:
positive
:
=
8
;
-- Width of the output pulse after edge detection
g_pulse_width
:
positive
:
=
1
);
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
len_i
:
in
std_logic_vector
(
g_glitch_len_width
-1
downto
0
);
data_i
:
in
std_logic
;
pulse_o
:
out
std_logic
);
end
entity
trigger_rcv
;
architecture
structural
of
trigger_rcv
is
signal
deglitched
:
std_logic
;
signal
rst_n
:
std_logic
;
component
gc_dyn_glitch_filt
is
generic
(
g_len_width
:
natural
);
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
len_i
:
in
std_logic_vector
(
g_len_width
-1
downto
0
);
dat_i
:
in
std_logic
;
dat_o
:
out
std_logic
);
end
component
gc_dyn_glitch_filt
;
component
gc_extend_pulse
is
generic
(
g_width
:
natural
);
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
pulse_i
:
in
std_logic
;
extended_o
:
out
std_logic
:
=
'0'
);
end
component
gc_extend_pulse
;
begin
rst_n
<=
not
(
rst_i
);
cmp_deglitcher
:
gc_dyn_glitch_filt
generic
map
(
g_len_width
=>
g_glitch_len_width
)
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
rst_n
,
len_i
=>
len_i
,
dat_i
=>
data_i
,
dat_o
=>
deglitched
);
cmp_edge_detector
:
gc_extend_pulse
generic
map
(
g_width
=>
g_pulse_width
)
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
rst_n
,
pulse_i
=>
deglitched
,
extended_o
=>
pulse_o
);
end
architecture
structural
;
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