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Commit a74b56fc authored by Adrian Byszuk's avatar Adrian Byszuk
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Add Wishbone endpoint support: 64 bit data width, no granularity, 29 bit address… 

Add Wishbone endpoint support: 64 bit data width, no granularity, 29 bit address width. Also, fix some SDRAM data issues.
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hdl/modules/pcie/common/DMA_FSM.vhd
View file @ a74b56fc
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: DMA_FSM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: DMA_FSM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- The state machine controls the DMA routine, writes the channel
-- buffer, as well as outputs DMA stata.
--
-- Dependencies:
-- Dependencies:
--
-- Revision 1.00 - Created. 25.07.2007
--
-- Additional Comments:
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
......@@ -123,28 +123,28 @@ architecture Behavioral of DMA_FSM is
, dmaST_Snout
-- dmaST_Stomp: after every ChBuf write, pause a clock before taking
-- next write. This state checks the availability of
-- next write. This state checks the availability of
-- the ChBuf (channel buffer) for write.
, dmaST_Stomp
-- dmaST_Body: TLP's in the middle, always integeral of MAX_SIZE.
, dmaST_Body
-- dmaST_Tail: the last TLP, similar with the 1st one, whose size
-- dmaST_Tail: the last TLP, similar with the 1st one, whose size
-- should be specially calculated.
, dmaST_Tail
-- -- dmaST_Before_Dex: before writing the MRd TLP (for next descriptor)
-- -- information for the next descriptor (if any),
-- -- information for the next descriptor (if any),
-- -- a pause is needed to wait for the ChBuf available.
-- , dmaST_Before_Dex
-- dmaST_NextDex: writing the descriptor MRd TLP information to
-- dmaST_NextDex: writing the descriptor MRd TLP information to
-- the ChBuf.
, dmaST_NextDex
-- dmaST_Await_Dex: after MRd(descriptor) info is written in the ChBuf,
-- the state machine waits for the descriptor's
-- dmaST_Await_Dex: after MRd(descriptor) info is written in the ChBuf,
-- the state machine waits for the descriptor's
-- arrival.
, dmaST_Await_Dex
);
......@@ -248,7 +248,7 @@ begin
-- -----------------------------------------
-- Syn_Delay: DMA_Start
-- DMA_Start2
--
--
Syn_Delay_DMA_Starts :
process (dma_clk)
begin
......@@ -263,9 +263,9 @@ begin
---- -----------------------------------------
---- -----------------------------------------
----
----
-- States synchronous: DMA
----
----
Syn_DMA_States :
process (dma_clk, dma_reset)
begin
......@@ -432,7 +432,7 @@ begin
-- -------------------------------------------------------------
-- Synchronous reg:
-- Synchronous reg:
-- State_Is_LoadParam
-- State_Is_Snout
-- State_Is_Body
......@@ -488,7 +488,7 @@ begin
-------------------------------------------------------------------
-- Synchronous Output: DMA_Abstract_Buffer_Write
--
--
-- DMA Channel (downstream and upstream) Buffers (128-bit) definition:
-- Note: Type not shows in this buffer
--
......@@ -499,14 +499,14 @@ begin
-- 93 ~ 30 : Host Address
-- 29 ~ 27 : BAR number
-- 26 ~ 19 : Tag
--
--
-- 18 ~ 17 : Format
-- 16 ~ 14 : TC
-- 13 : TD
-- 12 : EP
-- 11 ~ 10 : Attribute
-- 9 ~ 0 : Length
--
--
FSM_DMA_Abstract_Buffer_Write :
process (dma_clk, dma_reset)
begin
......@@ -542,7 +542,7 @@ begin
ChBuf_WrDin_i <= (others => '0'); -- must be the first argument
ChBuf_WrDin_i(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT) <= DMA_HA_Var;
if DMA_BAR_Number = CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT) <= DMA_PA_Loaded(C_EP_AWIDTH-1 downto 0);
ChBuf_WrDin_i(C_CHBUF_WB_BIT_TOP downto C_CHBUF_WB_BIT_BOT) <= DMA_PA_Loaded(C_WB_AWIDTH-1 downto 0);
elsif DMA_BAR_Number = CONV_STD_LOGIC_VECTOR(CINT_BRAM_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= DMA_PA_Loaded(C_PRAM_AWIDTH-1+2 downto 0);
elsif DMA_BAR_Number = CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
......@@ -556,7 +556,7 @@ begin
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_TOP) <= TLP_Has_Payload;
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_BOT) <= TLP_Hdr_is_4DW;
if DMA_BAR_Number = CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Snout_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 3) & '0';
else
......@@ -575,7 +575,7 @@ begin
ChBuf_WrDin_i <= (others => '0'); -- must be the first argument
ChBuf_WrDin_i(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT) <= DMA_HA_Var;
if DMA_BAR_Number = CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT) <= DMA_PA_Var(C_EP_AWIDTH-1 downto 0);
ChBuf_WrDin_i(C_CHBUF_WB_BIT_TOP downto C_CHBUF_WB_BIT_BOT) <= DMA_PA_Var(C_WB_AWIDTH-1 downto 0);
elsif DMA_BAR_Number = CONV_STD_LOGIC_VECTOR(CINT_BRAM_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= DMA_PA_Var(C_PRAM_AWIDTH-1+2 downto 0);
elsif DMA_BAR_Number = CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
......@@ -589,9 +589,9 @@ begin
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_TOP) <= TLP_Has_Payload;
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_BOT) <= TLP_Hdr_is_4DW;
if DMA_BAR_Number = CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Body_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 3) & '0';
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Body_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 3) & '0';
else
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Body_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2);
end if;
......@@ -609,7 +609,7 @@ begin
ChBuf_WrDin_i <= (others => '0'); -- must be the first argument
ChBuf_WrDin_i(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT) <= DMA_HA_Var;
if DMA_BAR_Number = CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT) <= DMA_PA_Var(C_EP_AWIDTH-1 downto 0);
ChBuf_WrDin_i(C_CHBUF_WB_BIT_TOP downto C_CHBUF_WB_BIT_BOT) <= DMA_PA_Var(C_WB_AWIDTH-1 downto 0);
elsif DMA_BAR_Number = CONV_STD_LOGIC_VECTOR(CINT_BRAM_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= DMA_PA_Var(C_PRAM_AWIDTH-1+2 downto 0);
elsif DMA_BAR_Number = CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
......@@ -623,7 +623,7 @@ begin
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_TOP) <= TLP_Has_Payload;
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_BOT) <= TLP_Hdr_is_4DW;
if DMA_BAR_Number = CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 3) & '0';
else
......@@ -651,7 +651,7 @@ begin
-- ----------------------------------------------
-- Synchronous Latch: BDA_nAligned_i
-- : Capture design defect
--
--
Latch_BDA_nAligned :
process (dma_clk, dma_reset)
begin
......
hdl/modules/pcie/common/FIFO_Wrapper.vhd deleted 100644 → 0
View file @ ee3a552e
----------------------------------------------------------------------------------
-- Company: ZITI
-- Engineer: wgao
--
-- Create Date: 16:37:22 12 Feb 2009
-- Design Name:
-- Module Name: eb_wrapper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity eb_wrapper is
generic (
C_ASYNFIFO_WIDTH : integer := 72
);
port (
--FIFO PCIe-->USER
H2B_wr_clk : in std_logic;
H2B_wr_en : in std_logic;
H2B_wr_din : in std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
H2B_wr_pfull : out std_logic;
H2B_wr_full : out std_logic;
H2B_wr_data_count : out std_logic_vector(C_EMU_FIFO_DC_WIDTH-1 downto 0);
H2B_rd_clk : in std_logic;
H2B_rd_en : in std_logic;
H2B_rd_dout : out std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
H2B_rd_pempty : out std_logic;
H2B_rd_empty : out std_logic;
H2B_rd_data_count : out std_logic_vector(C_EMU_FIFO_DC_WIDTH-1 downto 0);
H2B_rd_valid : out std_logic;
--FIFO USER-->PCIe
B2H_wr_clk : in std_logic;
B2H_wr_en : in std_logic;
B2H_wr_din : in std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
B2H_wr_pfull : out std_logic;
B2H_wr_full : out std_logic;
B2H_wr_data_count : out std_logic_vector(C_EMU_FIFO_DC_WIDTH-1 downto 0);
B2H_rd_clk : in std_logic;
B2H_rd_en : in std_logic;
B2H_rd_dout : out std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
B2H_rd_pempty : out std_logic;
B2H_rd_empty : out std_logic;
B2H_rd_data_count : out std_logic_vector(C_EMU_FIFO_DC_WIDTH-1 downto 0);
B2H_rd_valid : out std_logic;
--RESET from PCIe
rst : in std_logic
);
end entity eb_wrapper;
architecture Behavioral of eb_wrapper is
--- 32768 x 64, with data count synchronized to rd_clk
component eb_fifo_counted_resized
port (
wr_clk : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(C_ASYNFIFO_WIDTH-1-8 downto 0);
prog_full : out std_logic;
full : out std_logic;
rd_clk : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(C_ASYNFIFO_WIDTH-1-8 downto 0);
prog_empty : out std_logic;
empty : out std_logic;
rd_data_count : out std_logic_vector(C_EMU_FIFO_DC_WIDTH-1 downto 0);
wr_data_count : out std_logic_vector(C_EMU_FIFO_DC_WIDTH-1 downto 0);
valid : out std_logic;
rst : in std_logic
);
end component;
signal B2H_rd_data_count_wire : std_logic_vector(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal B2H_rd_data_count_i : std_logic_vector(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal H2B_rd_data_count_wire : std_logic_vector(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal H2B_rd_data_count_i : std_logic_vector(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal B2H_wr_data_count_wire : std_logic_vector(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal B2H_wr_data_count_i : std_logic_vector(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal H2B_wr_data_count_wire : std_logic_vector(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal H2B_wr_data_count_i : std_logic_vector(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal resized_H2B_wr_din : std_logic_vector(64-1 downto 0);
signal resized_H2B_rd_dout : std_logic_vector(64-1 downto 0);
signal resized_B2H_wr_din : std_logic_vector(64-1 downto 0);
signal resized_B2H_rd_dout : std_logic_vector(64-1 downto 0);
begin
B2H_rd_data_count <= B2H_rd_data_count_i;
H2B_rd_data_count <= H2B_rd_data_count_i;
B2H_wr_data_count <= B2H_wr_data_count_i;
H2B_wr_data_count <= H2B_wr_data_count_i;
resized_H2B_wr_din <= H2B_wr_din(64-1 downto 0);
resized_B2H_wr_din <= B2H_wr_din(64-1 downto 0);
H2B_rd_dout(71 downto 64) <= C_ALL_ZEROS(71 downto 64);
H2B_rd_dout(63 downto 0) <= resized_H2B_rd_dout;
B2H_rd_dout(71 downto 64) <= C_ALL_ZEROS(71 downto 64);
B2H_rd_dout(63 downto 0) <= resized_B2H_rd_dout;
-- ------------------------------------------
Syn_B2H_rd_data_count :
process (B2H_rd_clk)
begin
if B2H_rd_clk'event and B2H_rd_clk = '1' then
B2H_rd_data_count_i <= B2H_rd_data_count_wire;
end if;
end process;
Syn_H2B_rd_data_count :
process (H2B_rd_clk)
begin
if H2B_rd_clk'event and H2B_rd_clk = '1' then
H2B_rd_data_count_i <= H2B_rd_data_count_wire;
end if;
end process;
Syn_H2B_wr_data_count :
process (H2B_wr_clk)
begin
if H2B_wr_clk'event and H2B_wr_clk = '1' then
H2B_wr_data_count_i <= H2B_wr_data_count_wire;
end if;
end process;
Syn_B2H_wr_data_count :
process (B2H_wr_clk)
begin
if B2H_wr_clk'event and B2H_wr_clk = '1' then
B2H_wr_data_count_i <= B2H_wr_data_count_wire;
end if;
end process;
-- ------------------------------------------
----- Host2Board FIFO ----------
U0_H2B :
eb_fifo_counted_resized
port map (
wr_clk => H2B_wr_clk ,
wr_en => H2B_wr_en ,
din => resized_H2B_wr_din ,
prog_full => H2B_wr_pfull ,
full => H2B_wr_full ,
rd_clk => H2B_rd_clk ,
rd_en => H2B_rd_en ,
dout => resized_H2B_rd_dout ,
prog_empty => H2B_rd_pempty ,
empty => H2B_rd_empty ,
rd_data_count => H2B_rd_data_count_wire ,
wr_data_count => H2B_wr_data_count_wire ,
valid => H2B_rd_valid ,
rst => rst
);
----- Board2Host FIFO ----------
U0_B2H :
eb_fifo_counted_resized
port map (
wr_clk => B2H_wr_clk ,
wr_en => B2H_wr_en ,
din => resized_B2H_wr_din ,
prog_full => B2H_wr_pfull ,
full => B2H_wr_full ,
rd_clk => B2H_rd_clk ,
rd_en => B2H_rd_en ,
dout => resized_B2H_rd_dout ,
prog_empty => B2H_rd_pempty ,
empty => B2H_rd_empty ,
rd_data_count => B2H_rd_data_count_wire ,
wr_data_count => B2H_wr_data_count_wire ,
valid => B2H_rd_valid ,
rst => rst
);
end architecture Behavioral;
hdl/modules/pcie/common/FIFO_Wrapper_Loopback.vhd deleted 100644 → 0
View file @ ee3a552e
----------------------------------------------------------------------------------
-- Company: ZITI
-- Engineer: wgao
--
-- Create Date: 16:37:22 12 Feb 2009
-- Design Name:
-- Module Name: eb_wrapper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity eb_wrapper_loopback is
generic (
C_ASYNFIFO_WIDTH : integer := 72
);
port (
wr_clk : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
pfull : out std_logic;
full : out std_logic;
rd_clk : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
pempty : out std_logic;
empty : out std_logic;
data_count : out std_logic_vector(C_EMU_FIFO_DC_WIDTH-1 downto 0);
rst : in std_logic
);
end entity eb_wrapper_loopback;
architecture Behavioral of eb_wrapper_loopback is
--- 16384 x 72
component eb_fifo
port (
wr_clk : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
prog_full : out std_logic;
full : out std_logic;
rd_clk : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
prog_empty : out std_logic;
empty : out std_logic;
rst : in std_logic
);
end component;
--- 16384 x 64, with data count synchronized to rd_clk
component eb_fifo_counted_resized
port (
wr_clk : in std_logic;
wr_en : in std_logic;
din : in std_logic_vector(C_ASYNFIFO_WIDTH-1-8 downto 0);
prog_full : out std_logic;
full : out std_logic;
rd_clk : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(C_ASYNFIFO_WIDTH-1-8 downto 0);
prog_empty : out std_logic;
empty : out std_logic;
rd_data_count : out std_logic_vector(C_EMU_FIFO_DC_WIDTH-1 downto 0);
rst : in std_logic
);
end component;
signal data_count_wire : std_logic_vector(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal data_count_i : std_logic_vector(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal my_din : std_logic_vector(64-1 downto 0);
signal my_dout : std_logic_vector(64-1 downto 0);
begin
data_count <= data_count_i;
my_din <= din(64-1 downto 0);
dout(71 downto 64) <= C_ALL_ZEROS(71 downto 64);
dout(63 downto 0) <= my_dout;
-- ------------------------------------------
Syn_EB_FIFO_data_count :
process (rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
data_count_i <= data_count_wire;
end if;
end process;
-- ------------------------------------------
U0 :
eb_fifo_counted_resized
port map (
wr_clk => wr_clk ,
wr_en => wr_en ,
din => my_din ,
prog_full => pfull ,
full => full ,
rd_clk => rd_clk ,
rd_en => rd_en ,
dout => my_dout ,
prog_empty => pempty ,
empty => empty ,
rd_data_count => data_count_wire ,
rst => rst
);
end architecture Behavioral;
hdl/modules/pcie/common/Manifest.py
View file @ a74b56fc
......@@ -3,8 +3,6 @@ files = ["v6abb64Package_efifo_elink.vhd",
"DMA_Calculate.vhd",
"DMA_FSM.vhd",
"FF_tagram64x36.vhd",
"FIFO_Wrapper.vhd",
"FIFO_Wrapper_Loopback.vhd",
"Interrupts.vhd",
"PCIe_UserLogic_00.vhd",
"Registers.vhd",
......@@ -21,4 +19,6 @@ files = ["v6abb64Package_efifo_elink.vhd",
"rx_usDMA_Channel.vhd",
"tlpControl.vhd",
"tx_Mem_Reader.vhd",
"tx_Transact.vhd"]
"tx_Transact.vhd",
"wb_transact.vhd",
"wb_mem.vhd"]
hdl/modules/pcie/common/rx_CplD_Channel.vhd
View file @ a74b56fc
This diff is collapsed.
hdl/modules/pcie/common/rx_MWr_Channel.vhd
View file @ a74b56fc
This diff is collapsed.
hdl/modules/pcie/common/rx_Transact.vhd
View file @ a74b56fc
This diff is collapsed.
hdl/modules/pcie/common/rx_usDMA_Channel.vhd
View file @ a74b56fc
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: usDMA_Transact - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- Company:
-- Engineer:
--
-- Dependencies:
-- Design Name:
-- Module Name: usDMA_Transact - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision 1.20 - DMA engine shared out. 12.02.2007
--
......@@ -20,8 +20,8 @@
-- Revision 1.02 - FIFO added. 20.12.2006
--
-- Revision 1.00 - first release. 14.12.2006
--
-- Additional Comments:
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
......@@ -142,7 +142,7 @@ architecture Behavioral of usDMA_Transact is
DMA_PA_Snout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BAR_Number : out std_logic_vector(C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0);
--
--
DMA_Snout_Length : out std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Body_Length : out std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Tail_Length : out std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
......@@ -490,11 +490,11 @@ begin
usChBuf_ValidRd <= usTlp_RE; -- usTlp_RE_i and not usTlp_empty_i;
-- -------------------------------------------------
--
--
DMA_us_Status <= DMA_Status_i;
--
--
-- Synchronous output: DMA_Status_i
--
--
US_DMA_Status_Concat :
process (user_clk, Local_Reset_i)
begin
......@@ -562,7 +562,7 @@ begin
-- ---------------------------------------------
-- Synchronous delay
--
--
Synch_Delay_ren_Qout :
process (Local_Reset_i, user_clk)
begin
......@@ -594,7 +594,7 @@ begin
-- ---------------------------------------------
-- Request for arbitration
--
--
Synch_Req_Proc :
process (Local_Reset_i, user_clk)
begin
......@@ -624,20 +624,9 @@ begin
FSM_REQ_us <= REQST_Decision;
when REQST_Decision =>
if usTlp_Qout_wire(C_CHBUF_FMT_BIT_TOP) = '1' -- Has Payload
and usTlp_Qout_wire(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT)
= CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER)
then
usTlp_RE_i <= '0';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_Quantity;
else
usTlp_RE_i <= '0';
usTlp_Req_i <= not usDMA_Stop
and not usDMA_Stop2
and not us_FC_stop;
FSM_REQ_us <= REQST_nFIFO_Req;
end if;
usTlp_RE_i <= '0';
usTlp_Req_i <= not usDMA_Stop and not usDMA_Stop2 and not us_FC_stop;
FSM_REQ_us <= REQST_nFIFO_Req;
when REQST_nFIFO_Req =>
if usTlp_RE = '1' then
......@@ -702,7 +691,7 @@ begin
-- ---------------------------------------------
-- Sending usTlp_Qout
--
--
Synch_usTlp_Qout :
process (Local_Reset_i, user_clk)
begin
......@@ -722,7 +711,7 @@ begin
-- ---------------------------------------------
-- Delay of Empty and prog_Full
--
--
Synch_Delay_empty_and_full :
process (user_clk)
begin
......@@ -734,7 +723,7 @@ begin
usTlp_empty_r3 <= usTlp_empty_r2;
usTlp_empty_r4 <= usTlp_empty_r3;
usTlp_prog_Full_r1 <= usTlp_prog_Full;
-- usTlp_Req_i <= not usTlp_empty_i
-- usTlp_Req_i <= not usTlp_empty_i
-- and not usDMA_Stop
-- and not usDMA_Stop2
-- and not us_FC_stop
......
hdl/modules/pcie/common/tlpControl.vhd
View file @ a74b56fc
This diff is collapsed.
hdl/modules/pcie/common/tx_Mem_Reader.vhd
View file @ a74b56fc
This diff is collapsed.
hdl/modules/pcie/common/tx_Transact.vhd
View file @ a74b56fc
This diff is collapsed.
hdl/modules/pcie/common/v6abb64Package_efifo_elink.vhd
View file @ a74b56fc
......@@ -121,7 +121,10 @@ package abb64Package is
constant C_DDR_DATAWIDTH : integer range 32 to 512 := 512;
--- Block RAM address bus width. Variation requires BRAM core regeneration.
constant C_PRAM_AWIDTH : integer range 8 to 28 := 12;
constant C_PRAM_AWIDTH : integer range 8 to 29 := 29;
-- Wishbone endpoint address width
constant C_WB_AWIDTH : integer range 24 to 31 := 31;
--- Width for Interrupt generation counter
constant C_CNT_GINT_WIDTH : integer := 30;
......@@ -371,15 +374,17 @@ package abb64Package is
constant C_CHBUF_PA_BIT_BOT : integer := C_CHANNEL_BUF_WIDTH-C_EP_AWIDTH; --112;
constant C_CHBUF_PA_BIT_TOP : integer := C_CHANNEL_BUF_WIDTH-1; --127;
-- Bit range of BRAM address in Channel Buffer word
constant C_CHBUF_MA_BIT_BOT : integer := C_CHANNEL_BUF_WIDTH-C_PRAM_AWIDTH-2; --114;
constant C_CHBUF_MA_BIT_BOT : integer := C_CHANNEL_BUF_WIDTH-C_PRAM_AWIDTH-2; --97;
constant C_CHBUF_MA_BIT_TOP : integer := C_CHANNEL_BUF_WIDTH-1; --127;
-- Bit range of DDR address in Channel Buffer word
constant C_CHBUF_DDA_BIT_BOT : integer := C_CHANNEL_BUF_WIDTH-C_DDR_IAWIDTH; --102;
constant C_CHBUF_DDA_BIT_TOP : integer := C_CHANNEL_BUF_WIDTH-1; --127;
-- Bit range of Wishbone address in Channel Buffer word
constant C_CHBUF_WB_BIT_BOT : integer := C_CHANNEL_BUF_WIDTH-C_WB_AWIDTH; --97;
constant C_CHBUF_WB_BIT_TOP : integer := C_CHANNEL_BUF_WIDTH-1; --127;
------------------------------------------------------------------------
-- The Relaxed Ordering bit constant in TLP
constant C_RELAXED_ORDERING : std_logic := '0';
......
hdl/modules/pcie/common/wb_mem.vhd 0 → 100644
View file @ a74b56fc
-- -----------------------------------------
--
-- Simple generic wishbone memory module
--
-- Created by: abyszuk
--
--------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity WB_MEM is
generic(
AWIDTH : natural range 2 to 29;
DWIDTH : natural range 8 to 128
);
port(
-- WISHBONE SLAVE interface:
-- Single-Port RAM with Asynchronous Read
--
CLK_I : in std_logic;
ACK_O : out std_logic;
ADR_I : in std_logic_vector(AWIDTH-1 downto 0);
DAT_I : in std_logic_vector(DWIDTH-1 downto 0);
DAT_O : out std_logic_vector(DWIDTH-1 downto 0);
STB_I : in std_logic;
WE_I : in std_logic
);
end entity WB_MEM;
architecture rtl of WB_MEM is
type ram_type is array (2**AWIDTH downto 0) of std_logic_vector(DWIDTH-1 downto 0);
signal RAM : ram_type;
begin
REG: process(CLK_I)
begin
if(rising_edge(CLK_I)) then
if((STB_I and WE_I) = '1') then
RAM(to_integer(unsigned(ADR_I))) <= DAT_I;
end if;
end if;
end process REG;
ACK_O <= STB_I;
DAT_O <= RAM(to_integer(unsigned(ADR_I)));
end architecture rtl;
hdl/modules/pcie/common/wb_transact.vhd 0 → 100644
View file @ a74b56fc
This diff is collapsed.
hdl/testbench/pcie/Makefile
View file @ a74b56fc
......@@ -210,14 +210,12 @@ VHDL_SRC := ../../ip_cores/pcie/7k325ffg900/bram_x64.vhd \
../../ip_cores/pcie/7k325ffg900/mbuf_128x72.vhd \
../../ip_cores/pcie/7k325ffg900/prime_FIFO_plain.vhd \
../../ip_cores/pcie/7k325ffg900/sfifo_15x128.vhd \
../../top/pcie/bpm_pcie_k7.vhd \
../../modules/pcie/common/v6abb64Package_efifo_elink.vhd \
../../top/pcie/bpm_pcie_k7.vhd \
../../modules/pcie/common/DDR_Blinker.vhd \
../../modules/pcie/common/DMA_Calculate.vhd \
../../modules/pcie/common/DMA_FSM.vhd \
../../modules/pcie/common/FF_tagram64x36.vhd \
../../modules/pcie/common/FIFO_Wrapper.vhd \
../../modules/pcie/common/FIFO_Wrapper_Loopback.vhd \
../../modules/pcie/common/Interrupts.vhd \
../../modules/pcie/common/PCIe_UserLogic_00.vhd \
../../modules/pcie/common/Registers.vhd \
......@@ -235,6 +233,8 @@ VHDL_SRC := ../../ip_cores/pcie/7k325ffg900/bram_x64.vhd \
../../modules/pcie/common/tlpControl.vhd \
../../modules/pcie/common/tx_Mem_Reader.vhd \
../../modules/pcie/common/tx_Transact.vhd \
../../modules/pcie/common/wb_transact.vhd \
../../modules/pcie/common/wb_mem.vhd \
../../ip_cores/pcie/7k325ffg900/ddr_core/user_design/rtl/ddr_core.vhd \
../../ip_cores/pcie/7k325ffg900/ddr_core/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_top.vhd \
......@@ -243,14 +243,12 @@ work/eb_fifo_counted_resized/.eb_fifo_counted_resized_vhd \
work/mbuf_128x72/.mbuf_128x72_vhd \
work/prime_FIFO_plain/.prime_FIFO_plain_vhd \
work/sfifo_15x128/.sfifo_15x128_vhd \
work/bpm_pcie_k7/.bpm_pcie_k7_vhd \
work/v6abb64Package_efifo_elink/.v6abb64Package_efifo_elink_vhd \
work/bpm_pcie_k7/.bpm_pcie_k7_vhd \
work/DDR_Blinker/.DDR_Blinker_vhd \
work/DMA_Calculate/.DMA_Calculate_vhd \
work/DMA_FSM/.DMA_FSM_vhd \
work/FF_tagram64x36/.FF_tagram64x36_vhd \
work/FIFO_Wrapper/.FIFO_Wrapper_vhd \
work/FIFO_Wrapper_Loopback/.FIFO_Wrapper_Loopback_vhd \
work/Interrupts/.Interrupts_vhd \
work/PCIe_UserLogic_00/.PCIe_UserLogic_00_vhd \
work/Registers/.Registers_vhd \
......@@ -268,6 +266,8 @@ work/rx_usDMA_Channel/.rx_usDMA_Channel_vhd \
work/tlpControl/.tlpControl_vhd \
work/tx_Mem_Reader/.tx_Mem_Reader_vhd \
work/tx_Transact/.tx_Transact_vhd \
work/wb_transact/.wb_transact_vhd \
work/wb_mem/.wb_mem_vhd \
work/ddr_core/.ddr_core_vhd \
work/mig_7series_v1_8_ddr_phy_top/.mig_7series_v1_8_ddr_phy_top_vhd \
......@@ -275,7 +275,7 @@ LIBS := work
LIB_IND := work/.work
## rules #################################
sim: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): $(VHDL_OBJ)
$(VERILOG_OBJ): $(VHDL_OBJ)
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
......@@ -792,6 +792,10 @@ work/sfifo_15x128/.sfifo_15x128_vhd: ../../ip_cores/pcie/7k325ffg900/sfifo_15x12
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/v6abb64Package_efifo_elink/.v6abb64Package_efifo_elink_vhd: ../../modules/pcie/common/v6abb64Package_efifo_elink.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/bpm_pcie_k7/.bpm_pcie_k7_vhd: ../../top/pcie/bpm_pcie_k7.vhd
vcom $(VCOM_FLAGS) -work work $<
......@@ -801,10 +805,6 @@ work/bpm_pcie_k7/.bpm_pcie_k7_vhd: ../../top/pcie/bpm_pcie_k7.vhd
work/bpm_pcie_k7/.bpm_pcie_k7: \
work/v6abb64Package_efifo_elink/.v6abb64Package_efifo_elink
work/v6abb64Package_efifo_elink/.v6abb64Package_efifo_elink_vhd: ../../modules/pcie/common/v6abb64Package_efifo_elink.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/DDR_Blinker/.DDR_Blinker_vhd: ../../modules/pcie/common/DDR_Blinker.vhd
vcom $(VCOM_FLAGS) -work work $<
......@@ -838,22 +838,6 @@ work/FF_tagram64x36/.FF_tagram64x36_vhd: ../../modules/pcie/common/FF_tagram64x3
work/FF_tagram64x36/.FF_tagram64x36: \
work/v6abb64Package_efifo_elink/.v6abb64Package_efifo_elink
work/FIFO_Wrapper/.FIFO_Wrapper_vhd: ../../modules/pcie/common/FIFO_Wrapper.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/FIFO_Wrapper/.FIFO_Wrapper: \
work/v6abb64Package_efifo_elink/.v6abb64Package_efifo_elink
work/FIFO_Wrapper_Loopback/.FIFO_Wrapper_Loopback_vhd: ../../modules/pcie/common/FIFO_Wrapper_Loopback.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/FIFO_Wrapper_Loopback/.FIFO_Wrapper_Loopback: \
work/v6abb64Package_efifo_elink/.v6abb64Package_efifo_elink
work/Interrupts/.Interrupts_vhd: ../../modules/pcie/common/Interrupts.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......@@ -987,6 +971,19 @@ work/tx_Transact/.tx_Transact_vhd: ../../modules/pcie/common/tx_Transact.vhd
work/tx_Transact/.tx_Transact: \
work/v6abb64Package_efifo_elink/.v6abb64Package_efifo_elink
work/wb_transact/.wb_transact_vhd: ../../modules/pcie/common/wb_transact.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/wb_transact/.wb_transact: \
work/v6abb64Package_efifo_elink/.v6abb64Package_efifo_elink
work/wb_mem/.wb_mem_vhd: ../../modules/pcie/common/wb_mem.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/ddr_core/.ddr_core_vhd: ../../ip_cores/pcie/7k325ffg900/ddr_core/user_design/rtl/ddr_core.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......
hdl/testbench/pcie/tf64_pcie_axi.v
View file @ a74b56fc
......@@ -519,7 +519,7 @@ begin
// Multiple-descriptor case
//
$display("\n### DMA write & read BAR[2], Multiple-descriptor case ###\n");
board.DMA_PA = 'H789ABC;
board.DMA_PA = 'H789AB8;
board.DMA_HA = 'HDF0000;
board.DMA_BDA = 'H0BDABDA0;
board.DMA_Leng = 'H0208;
......@@ -534,7 +534,7 @@ begin
board.Hdr_Array[0] = `HEADER0_MWR3_ | board.Rx_TLP_Length[9:0];
board.Hdr_Array[1] = {`C_HOST_WRREQ_ID, board.Rx_MWr_Tag, 4'Hf, 4'Hf};
board.Hdr_Array[2] = `C_ADDR_DMA_DS_PAH;
dword_pack_data_store(-1, 0);
dword_pack_data_store(0, 0);
// Write PA_H
$display("%d ns: Write PA_H", $time);
......
hdl/top/pcie/bpm_pcie_k7.vhd
View file @ a74b56fc
This diff is collapsed.
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