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Beam Positoning Monitor - Gateware
Commit ac468cdd authored by Vitor Finotti's avatar Vitor Finotti Committed by Gustavo Bruno
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Renamed counter to avoid conflict with dsp-cores

parent ca0f5ac5
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Showing with 17 additions and 16 deletions
hdl/modules/dbe_common/Manifest.py
View file @ ac468cdd
modules = { "local" : ["reset_synch",
"pulse2level",
"trigger_rcv",
"counter"] };
"counter_simple"] };
files = [ "dbe_common_pkg.vhd" ];
hdl/modules/dbe_common/counter/counter.vhd → hdl/modules/dbe_common/counter_simple/counter_simple.vhd
View file @ ac468cdd
......@@ -6,7 +6,7 @@
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-11-11
-- Last update: 2015-11-18
-- Last update: 2015-12-10
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
......@@ -40,38 +40,39 @@ use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity counter is
entity counter_simple is
generic(
g_output_width : positive := 8
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_i : in std_logic;
ce_i : in std_logic;
up_i : in std_logic;
down_i : in std_logic;
count_o : out std_logic_vector(g_output_width-1 downto 0)
);
end counter;
end counter_simple;
architecture behavioural of counter is
architecture behavioural of counter_simple is
signal count : unsigned(g_output_width-1 downto 0) := to_unsigned(0, g_output_width);
begin
counter : process(clk_i)
counter_simple : process(clk_i)
begin
if clk_i = '1' and ce_i = '1' then
if rst_i = '1' then
if rising_edge(clk_i) then
if rst_n_i = '0' then
count <= to_unsigned(0, g_output_width);
else
if ce = '1' then
if up_i = '1' then
count <= count + 1;
elsif down_i = '1' then
count <= count - 1;
end if;
if up_i = '1' then
count <= count + 1;
elsif down_i = '1' then
count <= count - 1;
end if;
end if; --ce
end if; --rst
end if; -- clk
......
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