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Beam Positoning Monitor - Gateware
Commit af303789 authored by Lucas Russo's avatar Lucas Russo
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Merge branch 'dsp-devel' 

Conflicts:
	scripts/loader/program_fpga
parents 44058e47 b00b544d
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.gitmodules
View file @ af303789
......@@ -4,3 +4,6 @@
[submodule "hdl/ip_cores/etherbone-core"]
path = hdl/ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
[submodule "hdl/ip_cores/dsp-cores"]
path = hdl/ip_cores/dsp-cores
url = https://github.com/lerwys/dsp-cores.git
embedded-sw/Makefile
View file @ af303789
......@@ -89,7 +89,7 @@ $(OUTPUT).elf: $(OBJS)
./tools/genraminit $*.bin 0 > $@
%.vhd: tools %.bin
./tools/genramvhd -s 131072 $*.bin > $@
./tools/genramvhd -s 90112 $*.bin > $@
$(OBJS): include/board.h
......
embedded-sw/arch/lm32/ram.ld
View file @ af303789
......@@ -31,8 +31,8 @@ GROUP(-lgcc -lc)
MEMORY
{
/* ram : ORIGIN = 0x00000000, LENGTH = 0x16000 */
ram : ORIGIN = 0x00000000, LENGTH = 0x20000 /* 128KB */
ram : ORIGIN = 0x00000000, LENGTH = 0x16000 /* 90KB */
/* ram : ORIGIN = 0x00000000, LENGTH = 0x20000 */ /* 128KB */
}
SECTIONS
......
embedded-sw/dbe.vhd
View file @ af303789
This source diff could not be displayed because it is too large. You can view the blob instead.
embedded-sw/dbe_lwip.vhd 0 → 100644
View file @ af303789
This diff is collapsed.
embedded-sw/fmc/fmc516/fmc516.c
View file @ af303789
......@@ -71,22 +71,24 @@ void fmc516_init_regs(unsigned int id)
dbg_print("> Leds and clock select\n");
// No test data. External reference on. Led0 on. Led1 on. VCXO off
// No test data. External reference on. Led0 on. VCXO off
fmc516_clk_sel(id, 1);
fmc516_led1(id, 1);
fmc516_led0(id, 1);
// Adjsut the delays of all channels. Don't change these values
// Adjust the delays of all channels. Don't change these values
// unless you really have to!
fmc516_adj_delay(id, FMC516_ISLA216_ADC0, 5, 24, commit);
//fmc516_adj_delay(id, FMC516_ISLA216_ADC0, 5, 15, commit);
fmc516_adj_delay(id, FMC516_ISLA216_ADC1, 5, 14, commit);
fmc516_adj_delay(id, FMC516_ISLA216_ADC2, 5, 15, commit);
fmc516_adj_delay(id, FMC516_ISLA216_ADC3, 5, 25, commit);
//fmc516_adj_delay(id, FMC516_ISLA216_ADC3, 5, 25, commit);
fmc516_adj_delay(id, FMC516_ISLA216_ADC3, 5, 28, commit);
// Delay the falling edge of all channels
fmc516_fe_dly(id, FMC516_ISLA216_ADC0, 0, 0);
fmc516_fe_dly(id, FMC516_ISLA216_ADC1, 0, 0);
fmc516_fe_dly(id, FMC516_ISLA216_ADC2, 0, 0);
fmc516_fe_dly(id, FMC516_ISLA216_ADC3, 0, 0);
fmc516_fe_rg_dly(id, FMC516_ISLA216_ADC0, 0, 0, 0, 0);
fmc516_fe_rg_dly(id, FMC516_ISLA216_ADC1, 0, 0, 0, 0);
fmc516_fe_rg_dly(id, FMC516_ISLA216_ADC2, 0, 0, 0, 0);
fmc516_fe_rg_dly(id, FMC516_ISLA216_ADC3, 0, 0, 0, 0);
}
void fmc516_sweep_delays(unsigned int id)
......@@ -94,24 +96,24 @@ void fmc516_sweep_delays(unsigned int id)
int commit = 1;
int i, j;
dbg_print("> ADC%d data delay: %d...\n", 0, FMC516_CH0_CTL_DATA_CHAIN_DLY_R(fmc516[id]->CH0_CTL));
dbg_print("> ADC%d data delay: %d...\n", 1, FMC516_CH1_CTL_DATA_CHAIN_DLY_R(fmc516[id]->CH1_CTL));
dbg_print("> ADC%d data delay: %d...\n", 2, FMC516_CH2_CTL_DATA_CHAIN_DLY_R(fmc516[id]->CH2_CTL));
dbg_print("> ADC%d data delay: %d...\n", 3, FMC516_CH3_CTL_DATA_CHAIN_DLY_R(fmc516[id]->CH3_CTL));
dbg_print("> ADC%d data delay: %d...\n", 0, FMC516_CH0_FN_DLY_DATA_CHAIN_DLY_R(fmc516[id]->CH0_FN_DLY));
dbg_print("> ADC%d data delay: %d...\n", 1, FMC516_CH1_FN_DLY_DATA_CHAIN_DLY_R(fmc516[id]->CH1_FN_DLY));
dbg_print("> ADC%d data delay: %d...\n", 2, FMC516_CH2_FN_DLY_DATA_CHAIN_DLY_R(fmc516[id]->CH2_FN_DLY));
dbg_print("> ADC%d data delay: %d...\n", 3, FMC516_CH3_FN_DLY_DATA_CHAIN_DLY_R(fmc516[id]->CH3_FN_DLY));
//for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
//for (j = 0; j < 32; ++j) {
// dbg_print("> sweeping ADC%d clk delay values: %d...\n", 1, j);
// fmc516_adj_delay(id, FMC516_ISLA216_ADC1, -1, j, commit);
// delay(80000000);
// dbg_print("> ADC%d data delay: %d...\n", 0, FMC516_CH0_CTL_CLK_CHAIN_DLY_R(fmc516[id]->CH0_CTL));
// dbg_print("> ADC%d data delay: %d...\n", 0, FMC516_CH0_CTL_CLK_CHAIN_DLY_R(fmc516[id]->CH0_FN_DLY));
//}
//for (j = 0; j < 32; ++j) {
// dbg_print("> sweeping ADC%d clk delay values: %d...\n", 2, j);
// fmc516_adj_delay(id, FMC516_ISLA216_ADC2, -1, j, commit);
// delay(150000000);
// dbg_print("> ADC%d data delay: %d...\n", 2, FMC516_CH2_CTL_CLK_CHAIN_DLY_R(fmc516[id]->CH2_CTL));
// dbg_print("> ADC%d data delay: %d...\n", 2, FMC516_CH2_CTL_CLK_CHAIN_DLY_R(fmc516[id]->CH2_FN_DLY));
//}
//}
}
......@@ -134,20 +136,21 @@ void fmc516_adj_delay(unsigned int id, int ch, int clk_dly, int data_dly, int co
// Find the correct ADC instance to operate on
switch(ch) {
case FMC516_ISLA216_ADC0:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_FN_DLY;
break;
case FMC516_ISLA216_ADC1:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH1_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH1_FN_DLY;
break;
case FMC516_ISLA216_ADC2:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH2_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH2_FN_DLY;
break;
case FMC516_ISLA216_ADC3:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH3_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH3_FN_DLY;
break;
default:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_CTL;
dbg_print("> Unsupported FMC516 ADC channel\n");
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_FN_DLY;
}
// Read the register value once
......@@ -157,15 +160,15 @@ void fmc516_adj_delay(unsigned int id, int ch, int clk_dly, int data_dly, int co
/* All Read/Write macros are the same for all channels. Use the first one */
if (clk_dly != -1) {
/* Clear clk delay bits and write the desired value*/
adc_ctl_reg = (adc_ctl_reg & ~FMC516_CH0_CTL_CLK_CHAIN_DLY_MASK) |
FMC516_CH0_CTL_CLK_CHAIN_DLY_W(clk_dly);
adc_ctl_reg = (adc_ctl_reg & ~FMC516_CH0_FN_DLY_CLK_CHAIN_DLY_MASK) |
FMC516_CH0_FN_DLY_CLK_CHAIN_DLY_W(clk_dly);
}
if (data_dly != -1) {
/* Clear clk delay bits and write the desired value*/
adc_ctl_reg = (adc_ctl_reg & ~FMC516_CH0_CTL_DATA_CHAIN_DLY_MASK) |
FMC516_CH0_CTL_DATA_CHAIN_DLY_W(data_dly);
adc_ctl_reg = (adc_ctl_reg & ~FMC516_CH0_FN_DLY_DATA_CHAIN_DLY_MASK) |
FMC516_CH0_FN_DLY_DATA_CHAIN_DLY_W(data_dly);
}
......@@ -232,39 +235,56 @@ uint32_t fmc516_read_adc3(unsigned int id)
}
// ADC delay falling edge control
void fmc516_fe_dly(unsigned int id, int ch, int fe_dly_d1, int fe_dly_d2)
void fmc516_fe_rg_dly(unsigned int id, int ch, int fe_dly_d1, int fe_dly_d2,
int rg_dly_d1, int rg_dly_d2)
{
uint32_t *fmc_ch_handler;
uint32_t fe_dly_reg;
uint32_t dly_ctl_reg;
switch(ch) {
case FMC516_ISLA216_ADC0:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_DLY_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_CS_DLY;
break;
case FMC516_ISLA216_ADC1:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH1_DLY_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH1_CS_DLY;
break;
case FMC516_ISLA216_ADC2:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH2_DLY_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH2_CS_DLY;
break;
case FMC516_ISLA216_ADC3:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH3_DLY_CTL;
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH3_CS_DLY;
break;
default:
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_DLY_CTL;
dbg_print("> Unsupported FMC516 ADC channel\n");
fmc_ch_handler = (uint32_t *) &fmc516[id]->CH0_CS_DLY;
}
// Read register value once
fe_dly_reg = *fmc_ch_handler;
dly_ctl_reg = *fmc_ch_handler;
if (fe_dly_d2)
fe_dly_reg |= (fe_dly_reg & ~FMC516_CH0_DLY_CTL_FE_DLY_MASK) |
FMC516_CH0_DLY_CTL_FE_DLY_W(0x3);
dly_ctl_reg = (dly_ctl_reg & ~FMC516_CH0_CS_DLY_FE_DLY_MASK) |
FMC516_CH0_CS_DLY_FE_DLY_W(0x3);
else if (fe_dly_d1)
fe_dly_reg |= (fe_dly_reg & ~FMC516_CH0_DLY_CTL_FE_DLY_MASK) |
FMC516_CH0_DLY_CTL_FE_DLY_W(0x1);
dly_ctl_reg = (dly_ctl_reg & ~FMC516_CH0_CS_DLY_FE_DLY_MASK) |
FMC516_CH0_CS_DLY_FE_DLY_W(0x1);
else
dly_ctl_reg = (dly_ctl_reg & ~FMC516_CH0_CS_DLY_FE_DLY_MASK) |
FMC516_CH0_CS_DLY_FE_DLY_W(0x0);
if (rg_dly_d2)
dly_ctl_reg = (dly_ctl_reg & ~FMC516_CH0_CS_DLY_RG_DLY_MASK) |
FMC516_CH0_CS_DLY_RG_DLY_W(0x3);
else if (rg_dly_d1)
dly_ctl_reg = (dly_ctl_reg & ~FMC516_CH0_CS_DLY_RG_DLY_MASK) |
FMC516_CH0_CS_DLY_RG_DLY_W(0x1);
else
dly_ctl_reg = (dly_ctl_reg & ~FMC516_CH0_CS_DLY_RG_DLY_MASK) |
FMC516_CH0_CS_DLY_RG_DLY_W(0x0);
// Write register value once
*fmc_ch_handler = fe_dly_reg;
*fmc_ch_handler = dly_ctl_reg;
dbg_print("dly_ctl_reg, *fmc_ch_handler = %08X, %08X\n", dly_ctl_reg, *fmc_ch_handler);
}
embedded-sw/include/fmc/fmc516/fmc516.h
View file @ af303789
......@@ -42,5 +42,6 @@ uint32_t fmc516_read_adc1(unsigned int id);
uint32_t fmc516_read_adc2(unsigned int id);
uint32_t fmc516_read_adc3(unsigned int id);
void fmc516_fe_dly(unsigned int id, int ch, int fe_dly_d1, int fe_dly_d2);
void fmc516_fe_rg_dly(unsigned int id, int ch, int fe_dly_d1, int fe_dly_d2,
int rg_dly_d1, int rg_dly_d2);
embedded-sw/include/hw/wb_fmc516.h
View file @ af303789
This diff is collapsed.
hdl/Manifest.py
View file @ af303789
#fetchto = "ip_cores"
modules = { "local": [
"modules/custom_wishbone",
"modules/custom_common",
"modules/dbe_wishbone",
"modules/dbe_common",
"modules/rffe_top",
"modules/ethmac",
"modules/fabric",
"modules/fmc_adc_common",
"ip_cores/general-cores",
"ip_cores/etherbone-core",
"platform/virtex6/chipscope"]
"ip_cores/dsp-cores",
"platform/virtex6/chipscope",
"platform/virtex6/ip_cores"]
# "git" : [
# ]
};
dsp-cores @ acfc59d6
Subproject commit e2503503405f83d13b265d980a4c00dd74062953
Subproject commit acfc59d620619a0e6ce3b333236d44e4096dbb25
etherbone-core @ 541e5b83
Subproject commit 66a04ccc2516c81e5f51a34ba188e8bfc1d41671
Subproject commit 541e5b834123ad6a86325edf607c885069706f3f
general-cores @ 093d4d35
Subproject commit 5453aacbac8e923214c38a53423bf59c9da8d975
Subproject commit 093d4d355065d81e16306fd3bf4463d6a7272695
hdl/modules/custom_wishbone/wb_fmc516/Manifest.py deleted 100644 → 0
View file @ 44058e47
modules = { "local" : ["coregen"] };
files = [ "wb_fmc516.vhd", "xwb_fmc516.vhd", "fmc516_adc_clk.vhd",
"fmc516_adc_data.vhd", "fmc516_adc_buf.vhd", "fmc516_adc_iface.vhd",
"wbgen/wb_fmc516_regs_pkg.vhd", "wbgen/wb_fmc516_regs.vhd",
"fmc516_pkg.vhd"
];
hdl/modules/custom_wishbone/wb_fmc516/coregen/Manifest.py deleted 100644 → 0
View file @ 44058e47
# Select between synthesis or simulation components
if (action == "synthesis" ):
if(target == "xilinx" and syn_device[0:4].upper()=="XC6V"):
files = ["cdc_fifo.ngc", "adc_data_cdc_fifo.ngc", "cdc_fifo.vhd", "adc_data_cdc_fifo.vhd"];
else:
print "WARNING: Device not supported for synthesis using the FMC516 core!"
elif (action == "simulation"):
if (target == "xilinx"):
files = ["cdc_fifo.vhd", "adc_data_cdc_fifo.vhd"];
else:
print "WARNING: Device not supported for simulation using the FMC516 core!"
hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_buf.vhd deleted 100644 → 0
View file @ 44058e47
------------------------------------------------------------------------------
-- Title : Wishbone FMC516 ADC Interface
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2012-17-10
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: ADC differential buffers for clock and data
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-03-12 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.fmc516_pkg.all;
entity fmc516_adc_buf is
port
(
-----------------------------
-- External ports
-----------------------------
-- ADC clocks. One clock per ADC channel
adc_clk0_p_i : in std_logic;
adc_clk0_n_i : in std_logic;
adc_clk1_p_i : in std_logic;
adc_clk1_n_i : in std_logic;
adc_clk2_p_i : in std_logic;
adc_clk2_n_i : in std_logic;
adc_clk3_p_i : in std_logic;
adc_clk3_n_i : in std_logic;
-- DDR ADC data channels.
adc_data_ch0_p_i : in std_logic_vector(c_num_adc_bits/2 - 1 downto 0);
adc_data_ch0_n_i : in std_logic_vector(c_num_adc_bits/2 - 1 downto 0);
adc_data_ch1_p_i : in std_logic_vector(c_num_adc_bits/2 - 1 downto 0);
adc_data_ch1_n_i : in std_logic_vector(c_num_adc_bits/2 - 1 downto 0);
adc_data_ch2_p_i : in std_logic_vector(c_num_adc_bits/2 - 1 downto 0);
adc_data_ch2_n_i : in std_logic_vector(c_num_adc_bits/2 - 1 downto 0);
adc_data_ch3_p_i : in std_logic_vector(c_num_adc_bits/2 - 1 downto 0);
adc_data_ch3_n_i : in std_logic_vector(c_num_adc_bits/2 - 1 downto 0);
adc_clk0_o : out std_logic;
adc_clk1_o : out std_logic;
adc_clk2_o : out std_logic;
adc_clk3_o : out std_logic;
adc_data_ch0_o : out std_logic_vector(c_num_adc_bits/2 - 1 downto 0);
adc_data_ch1_o : out std_logic_vector(c_num_adc_bits/2 - 1 downto 0);
adc_data_ch2_o : out std_logic_vector(c_num_adc_bits/2 - 1 downto 0);
adc_data_ch3_o : out std_logic_vector(c_num_adc_bits/2 - 1 downto 0)
);
end fmc516_adc_buf;
architecture rtl of fmc516_adc_buf is
begin
-----------------------------
-- ADC clock signal datapath
-----------------------------
--cmp_ibufgds_adc_clk0 : ibufgds
-- An IBUGDS intructs the mapper to use the glabal clock nets
--(GCLK pins). Therefore, it gives an error for the following
-- clock topology components, like: BUFIO, BUFR and IODELAY
cmp_ibufds_adc_clk0 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_clk0_p_i,
ib => adc_clk0_n_i,
o => adc_clk0_o
);
cmp_ibufds_adc_clk1 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_clk1_p_i,
ib => adc_clk1_n_i,
o => adc_clk1_o
);
cmp_ibufds_adc_clk2 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_clk2_p_i,
ib => adc_clk2_n_i,
o => adc_clk2_o
);
cmp_ibufds_adc_clk3 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_clk3_p_i,
ib => adc_clk3_n_i,
o => adc_clk3_o
);
-----------------------------
-- ADC data signal datapath
-----------------------------
gen_adc_data_buf_ch0 : for i in 0 to (c_num_adc_bits/2)-1 generate
-- Diferential Clock Buffers for adc input
cmp_ibufds_adc_data_ch0 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_data_ch0_p_i(i),
ib => adc_data_ch0_n_i(i),
o => adc_data_ch0_o(i)
);
cmp_ibufds_adc_data_ch1 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_data_ch1_p_i(i),
ib => adc_data_ch1_n_i(i),
o => adc_data_ch1_o(i)
);
cmp_ibufds_adc_data_ch2 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_data_ch2_p_i(i),
ib => adc_data_ch2_n_i(i),
o => adc_data_ch2_o(i)
);
cmp_ibufds_adc_data_ch3 : ibufds
generic map(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map(
i => adc_data_ch3_p_i(i),
ib => adc_data_ch3_n_i(i),
o => adc_data_ch3_o(i)
);
end generate;
end rtl;
hdl/modules/custom_common/Manifest.py → hdl/modules/dbe_common/Manifest.py
View file @ af303789
modules = { "local" : ["reset_synch"] };
files = [ "custom_common_pkg.vhd" ];
files = [ "dbe_common_pkg.vhd" ];
hdl/modules/custom_common/custom_common_pkg.vhd → hdl/modules/dbe_common/dbe_common_pkg.vhd
View file @ af303789
library ieee;
use ieee.std_logic_1164.all;
package custom_common_pkg is
package dbe_common_pkg is
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component reset_synch
port
port
(
clk_i : in std_logic;
arst_n_i : in std_logic;
rst_n_o : out std_logic
);
end component;
end custom_common_pkg;
end dbe_common_pkg;
hdl/modules/custom_wishbone/Manifest.py → hdl/modules/dbe_wishbone/Manifest.py
View file @ af303789
files = [ "custom_wishbone_pkg.vhd" ];
files = [ "dbe_wishbone_pkg.vhd" ];
modules = { "local" : [
"wb_stream",
"wb_fmc150",
"wb_fmc516",
"wb_ethmac_adapter",
"wb_dbe_periph"
# "wb_fmc_iface"
"wb_fmc130m_4ch",
"wb_ethmac_adapter",
"wb_ethmac",
"wb_dbe_periph",
"wb_rs232_syscon"
] };
hdl/modules/custom_wishbone/wb_dbe_periph/wb_dbe_periph.vhd → hdl/modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd
View file @ af303789
......@@ -3,7 +3,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.custom_wishbone_pkg.all;
use work.dbe_wishbone_pkg.all;
use work.wishbone_pkg.all;
entity wb_dbe_periph is
......
hdl/modules/custom_wishbone/wb_dbe_periph/xwb_dbe_periph.vhd → hdl/modules/dbe_wishbone/wb_dbe_periph/xwb_dbe_periph.vhd
View file @ af303789
......@@ -3,7 +3,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.custom_wishbone_pkg.all;
use work.dbe_wishbone_pkg.all;
use work.wishbone_pkg.all;
entity xwb_dbe_periph is
......
hdl/modules/custom_wishbone/wb_dma_interface_FIX/wb_dma_interface.old.vhd → hdl/modules/dbe_wishbone/wb_dma_interface_FIX/wb_dma_interface.old.vhd
View file @ af303789
......@@ -10,8 +10,8 @@ library work;
use work.genram_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.custom_wishbone_pkg.all;
use work.custom_common_pkg.all;
use work.dbe_wishbone_pkg.all;
use work.dbe_common_pkg.all;
------------------------------------------------------------------------------
-- Entity section
......
hdl/modules/custom_wishbone/wb_dma_interface_FIX/wb_dma_interface.vhd → hdl/modules/dbe_wishbone/wb_dma_interface_FIX/wb_dma_interface.vhd
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......@@ -10,8 +10,8 @@ library work;
use work.genram_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.custom_wishbone_pkg.all;
use work.custom_common_pkg.all;
use work.dbe_wishbone_pkg.all;
use work.dbe_common_pkg.all;
------------------------------------------------------------------------------
-- Entity section
......
hdl/modules/custom_wishbone/wb_dma_interface_FIX/xwb_dma_interface.old.vhd → hdl/modules/dbe_wishbone/wb_dma_interface_FIX/xwb_dma_interface.old.vhd
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......@@ -8,7 +8,7 @@ use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.custom_wishbone_pkg.all;
use work.dbe_wishbone_pkg.all;
------------------------------------------------------------------------------
-- Entity section
......
hdl/modules/custom_wishbone/wb_dma_interface_FIX/xwb_dma_interface.vhd → hdl/modules/dbe_wishbone/wb_dma_interface_FIX/xwb_dma_interface.vhd
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......@@ -8,7 +8,7 @@ use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.custom_wishbone_pkg.all;
use work.dbe_wishbone_pkg.all;
------------------------------------------------------------------------------
-- Entity section
......
hdl/modules/dbe_wishbone/wb_fmc130m_4ch/Manifest.py 0 → 100644
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files = [ "wb_fmc130m_4ch.vhd",
"xwb_fmc130m_4ch.vhd",
"wbgen/fmc_130m_4ch_regs_pkg.vhd",
"wbgen/fmc_130m_4ch_regs.vhd"
];
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#!/bin/bash
wbgen2 -V fmc_130m_4ch_regs.vhd -H record -p fmc_130m_4ch_regs_pkg.vhd -K ../../../../sim/regs/wb_fmc130m_4ch_regs.vh -s struct -C fmc130m_4ch_regs.h -f html -D doc/fmc130m_4ch_regs_wb.html fmc_130m_4ch_regs.wb
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