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Commit b5ae2a89 authored by Lucas Russo's avatar Lucas Russo
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hdl/platform/artix7/*: add AXI4-Stream 2-to-1 muxer 

This will be the base (for now, at least) for the
multiplexed acquisition core.
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hdl/platform/artix7/ip_cores/Manifest.py 0 → 100644
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modules = {"local" : ["axis_mux_2_to_1"]}
hdl/platform/artix7/ip_cores/axis_mux_2_to_1.xco 0 → 100644
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hdl/platform/artix7/ip_cores/axis_mux_2_to_1.xise 0 → 100644
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hdl/platform/artix7/ip_cores/axis_mux_2_to_1/Manifest.py 0 → 100644
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if (action == "synthesis"):
files = ["axis_mux_2_to_1.ngc"]
else:
files = ["axis_mux_2_to_1.vhd"]
modules = {"local" : ["hdl/verilog"]}
hdl/platform/artix7/ip_cores/axis_mux_2_to_1/doc/axis_interconnect_v1_1_readme.txt 0 → 100644
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CHANGE LOG for AXI4-Stream Interconnect 1.1
Release Date: July 25, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURE HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
This file contains the change log for all released versions of the Xilinx
LogiCORE IP core AXI4-Stream Interconnect.
For the latest core updates, see the product page at:
http://www.xilinx.com/products/intellectual-property/axi4-stream_interconnect.htm
For installation instructions for this release, please go to:
www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements, see:
www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
2. DEVICE SUPPORT
2.1. ISE
The following device families are supported by the core for this release:
All Series 7 devices
All Virtex-6 devices
All Spartan-6 devices
2.2. VIVADO
The following device families are supported by the core for this release:
All Series 7 devices
3. NEW FEATURE HISTORY
3.1 ISE
v1.1
- Support for ACLKEN across clock converters and FIFO.
- Area improvements in data width convertrs.
- Enhanced GUI layout.
v1.0
- Initial Release
3.2 Vivado
v1.1
- Same features as for ISE.
v1.0
- Initial Release
4. RESOLVED ISSUES
4.1 ISE
- 2012/12/18 - Updated FIFO Generator instantiation to match the case of the verilog model.
4.2 Vivado
- 2012/12/18 - Updated FIFO Generator instantiation to match the case of the verilog model.
5. KNOWN ISSUES & LIMITATIONS
- None
- For a comprehensive listing of Known Issues for this core, please see the IP
Release Notes Guide,
www.xilinx.com/support/documentation/ip_documentation/axis_interconnect/v1_1/pg035_axis_interconnect.pdf
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Feedback on this IP core may also be submitted under the "Leave Feedback"
menu item in Vivado/PlanAhead.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
07/25/2012 Xilinx, Inc. 1.1 ISE 14.2 and Vivado 2012.2 support
04/24/2012 Xilinx, Inc. 1.0 ISE 14.1 support and Vivado 2012.1 beta
support, Initial Release
================================================================================
8. LEGAL DISCLAIMER
(c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
hdl/platform/artix7/ip_cores/axis_mux_2_to_1/doc/axis_interconnect_v1_1_vinfo.html 0 → 100644
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<HTML>
<HEAD>
<TITLE>axis_interconnect_v1_1_vinfo</TITLE>
<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
</HEAD>
<BODY>
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
CHANGE LOG for AXI4-Stream Interconnect 1.1
Release Date: July 25, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURE HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
This file contains the change log for all released versions of the Xilinx
LogiCORE IP core AXI4-Stream Interconnect.
For the latest core updates, see the product page at:
<A HREF="http://www.xilinx.com/products/intellectual-property/axi4-stream_interconnect.htm">www.xilinx.com/products/intellectual-property/axi4-stream_interconnect.htm</A>
For installation instructions for this release, please go to:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
For system requirements, see:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
2. DEVICE SUPPORT
2.1. ISE
The following device families are supported by the core for this release:
All Series 7 devices
All Virtex-6 devices
All Spartan-6 devices
2.2. VIVADO
The following device families are supported by the core for this release:
All Series 7 devices
3. NEW FEATURE HISTORY
3.1 ISE
v1.1
- Support for ACLKEN across clock converters and FIFO.
- Area improvements in data width convertrs.
- Enhanced GUI layout.
v1.0
- Initial Release
3.2 Vivado
v1.1
- Same features as for ISE.
v1.0
- Initial Release
4. RESOLVED ISSUES
4.1 ISE
- 2012/12/18 - Updated FIFO Generator instantiation to match the case of the verilog model.
4.2 Vivado
- 2012/12/18 - Updated FIFO Generator instantiation to match the case of the verilog model.
5. KNOWN ISSUES & LIMITATIONS
- None
- For a comprehensive listing of Known Issues for this core, please see the IP
Release Notes Guide,
<A HREF="http://www.xilinx.com/support/documentation/ip_documentation/axis_interconnect/v1_1/pg035_axis_interconnect.pdf">www.xilinx.com/support/documentation/ip_documentation/axis_interconnect/v1_1/pg035_axis_interconnect.pdf</A>
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
Questions are routed to a team with expertise using this product.
Feedback on this IP core may also be submitted under the "Leave Feedback"
menu item in Vivado/PlanAhead.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
07/25/2012 Xilinx, Inc. 1.1 ISE 14.2 and Vivado 2012.2 support
04/24/2012 Xilinx, Inc. 1.0 ISE 14.1 support and Vivado 2012.1 beta
support, Initial Release
================================================================================
8. LEGAL DISCLAIMER
(c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
</FONT>
</PRE>
</BODY>
</HTML>
hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/Manifest.py 0 → 100644
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files = [
"axis_interconnect_v1_1_arb_rr.v",
"axis_interconnect_v1_1_axisc_arb_responder.v",
"axis_interconnect_v1_1_axisc_decoder.v",
"axis_interconnect_v1_1_axisc_downsizer.v",
"axis_interconnect_v1_1_axis_clock_converter.v",
"axis_interconnect_v1_1_axisc_register_slice.v",
"axis_interconnect_v1_1_axisc_sample_cycle_ratio.v",
"axis_interconnect_v1_1_axisc_sync_clock_converter.v",
"axis_interconnect_v1_1_axisc_transfer_mux.v",
"axis_interconnect_v1_1_axisc_upsizer.v",
"axis_interconnect_v1_1_axis_data_fifo.v",
"axis_interconnect_v1_1_axis_dwidth_converter.v",
"axis_interconnect_v1_1_axis_interconnect_16x16_top.v",
"axis_interconnect_v1_1_axis_interconnect.v",
"axis_interconnect_v1_1_axis_register_slice.v",
"axis_interconnect_v1_1_axis_subset_converter.v",
"axis_interconnect_v1_1_axis_switch_arbiter.v",
"axis_interconnect_v1_1_axis_switch.v",
"axis_interconnect_v1_1_dynamic_datapath.v",
"axis_interconnect_v1_1_dynamic_priority_encoder.v",
"axis_interconnect_v1_1_mux_enc.v",
"axis_interconnect_v1_1_util_aclken_converter.v",
"axis_interconnect_v1_1_util_aclken_converter_wrapper.v",
"axis_interconnect_v1_1_util_axis2vector.v",
"axis_interconnect_v1_1_util_vector2axis.v"
]
hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_arb_rr.v 0 → 100644
View file @ b5ae2a89
// (c) Copyright 2011-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// arb_rr
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module axis_interconnect_v1_1_arb_rr #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex7",
parameter integer C_NUM_SI_SLOTS = 8,
parameter integer C_LOG_SI_SLOTS = 3,
parameter C_ARB_ALGORITHM = "ROUND_ROBIN"
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// System Signals
input wire ACLK,
input wire ARESET,
input wire ACLKEN,
input wire [C_NUM_SI_SLOTS-1:0] ARB_REQ,
input wire ARB_DONE,
output wire [C_NUM_SI_SLOTS-1:0] ARB_GNT,
output wire [C_LOG_SI_SLOTS-1:0] ARB_SEL
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
function [C_NUM_SI_SLOTS*C_LOG_SI_SLOTS-1:0] f_port_priority_init (
input integer num_slaves
);
begin : main
integer i;
for (i = 0; i < num_slaves; i = i + 1) begin
f_port_priority_init[i*C_LOG_SI_SLOTS+:C_LOG_SI_SLOTS] = i[C_LOG_SI_SLOTS-1:0];
end
end
endfunction
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire arb_busy_ns;
reg arb_busy_r;
wire advance;
wire [C_LOG_SI_SLOTS-1:0] barrel_cntr_ns;
reg [C_LOG_SI_SLOTS-1:0] barrel_cntr;
wire [C_NUM_SI_SLOTS-1:0] arb_req_rot;
wire [C_NUM_SI_SLOTS-1:0] arb_req_i;
reg [C_NUM_SI_SLOTS*C_LOG_SI_SLOTS-1:0] port_priority_r;
wire [C_NUM_SI_SLOTS*C_LOG_SI_SLOTS-1:0] port_priority_ns;
wire [C_LOG_SI_SLOTS-1:0] sel_i;
wire valid_i;
wire [C_LOG_SI_SLOTS-1:0] arb_sel_ns;
reg [C_LOG_SI_SLOTS-1:0] arb_sel_r;
wire [C_NUM_SI_SLOTS-1:0] sel_decode_i;
wire [C_NUM_SI_SLOTS-1:0] arb_gnt_ns;
reg [C_NUM_SI_SLOTS-1:0] arb_gnt_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// Generate busy logic. When arbiter is busy a new REQ can't be granted and
// priority will not advance.
assign arb_busy_ns = (valid_i) | (arb_busy_r & ~ARB_DONE);
always @(posedge ACLK) begin
if (ARESET) begin
arb_busy_r <= 1'b0;
end
else if (ACLKEN) begin
arb_busy_r <= arb_busy_ns;
end
end
assign advance = ~arb_busy_r | (|arb_gnt_r);
assign barrel_cntr_ns = (barrel_cntr == C_NUM_SI_SLOTS-1) ? {C_LOG_SI_SLOTS{1'b0}} : barrel_cntr + 1'b1 ;
always @(posedge ACLK) begin
if (ARESET) begin
barrel_cntr <= {C_LOG_SI_SLOTS{1'b0}};
end
else if (ACLKEN && C_ARB_ALGORITHM == "ROUND_ROBIN") begin
barrel_cntr <= advance ? barrel_cntr_ns : barrel_cntr;
end
end
assign arb_req_i = ARB_REQ & ~arb_gnt_r;
assign arb_req_rot[C_NUM_SI_SLOTS-1:0] = {arb_req_i, arb_req_i} >> barrel_cntr;
// Port Priority implements round robin arbitration
always @(posedge ACLK) begin
if (ARESET) begin
port_priority_r <= f_port_priority_init(C_NUM_SI_SLOTS);
end
else if (ACLKEN && (C_ARB_ALGORITHM == "ROUND_ROBIN")) begin
port_priority_r <= advance ? port_priority_ns : port_priority_r;
end
end
assign port_priority_ns[0+:(C_NUM_SI_SLOTS-1)*C_LOG_SI_SLOTS] =
port_priority_r[1*C_LOG_SI_SLOTS+:(C_NUM_SI_SLOTS-1)*C_LOG_SI_SLOTS];
assign port_priority_ns[(C_NUM_SI_SLOTS-1)*C_LOG_SI_SLOTS+:C_LOG_SI_SLOTS] = port_priority_r[0+:C_LOG_SI_SLOTS];
axis_interconnect_v1_1_dynamic_priority_encoder #(
.C_FAMILY ( C_FAMILY ) ,
.C_REQ_WIDTH ( C_NUM_SI_SLOTS ) ,
.C_ENC_WIDTH ( C_LOG_SI_SLOTS )
)
dynamic_priority_encoder_0
(
.REQ ( arb_req_rot ) ,
.PORT_PRIORITY ( port_priority_r ) ,
.SEL ( sel_i ) ,
.VALID ( valid_i )
);
assign arb_sel_ns = valid_i & (~arb_busy_r | ARB_DONE) ? sel_i : arb_sel_r;
always @(posedge ACLK) begin
if (ARESET) begin
arb_sel_r <= {C_LOG_SI_SLOTS{1'b0}};
end
else if (ACLKEN) begin
arb_sel_r <= arb_sel_ns;
end
end
assign ARB_SEL = arb_sel_r;
// Decode sel from integer to one-hot
generate
genvar i;
for (i = 0; i < C_NUM_SI_SLOTS; i = i + 1) begin : gen_sel_decode_one_hot
assign sel_decode_i[i] = (i == sel_i);
end
endgenerate
assign arb_gnt_ns = valid_i & (~arb_busy_r | ARB_DONE) ? sel_decode_i : {C_LOG_SI_SLOTS{1'b0}};
always @(posedge ACLK) begin
if (ARESET) begin
arb_gnt_r <= {C_LOG_SI_SLOTS{1'b0}};
end
else if (ACLKEN) begin
arb_gnt_r <= arb_gnt_ns;
end
end
assign ARB_GNT = arb_gnt_r;
endmodule // arb_rr
`default_nettype wire
hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_switch_arbiter.v 0 → 100644
View file @ b5ae2a89
// (c) Copyright 2011-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axis_switch_arbiter
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module axis_interconnect_v1_1_axis_switch_arbiter #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex7",
parameter integer C_NUM_SI_SLOTS = 8,
parameter integer C_LOG_SI_SLOTS = 3,
parameter integer C_NUM_MI_SLOTS = 2,
parameter C_ARB_ALGORITHM = "ROUND_ROBIN",
parameter C_SINGLE_SLAVE_CONNECTIVITY_ARRAY = {C_NUM_MI_SLOTS{1'b0}}
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// System Signals
input wire ACLK,
input wire ARESETN,
input wire ACLKEN,
input wire [C_NUM_MI_SLOTS*C_NUM_SI_SLOTS-1:0] ARB_REQ,
input wire [C_NUM_MI_SLOTS-1:0] ARB_DONE,
output wire [C_NUM_MI_SLOTS*C_NUM_SI_SLOTS-1:0] ARB_GNT,
output wire [C_NUM_MI_SLOTS*C_LOG_SI_SLOTS-1:0] ARB_SEL
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg areset;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
always @(posedge ACLK) begin
areset <= ~ARESETN;
end
generate
genvar i;
for (i = 0; i < C_NUM_MI_SLOTS; i = i + 1) begin : gen_mi_arb
if (C_SINGLE_SLAVE_CONNECTIVITY_ARRAY[i]) begin : gen_arb_tie_off
assign ARB_GNT [i*C_NUM_SI_SLOTS+:C_NUM_SI_SLOTS] = ARB_REQ[i*C_NUM_SI_SLOTS+:C_NUM_SI_SLOTS];
assign ARB_SEL [i*C_LOG_SI_SLOTS+:C_LOG_SI_SLOTS] = {C_LOG_SI_SLOTS{1'b0}};
end else if (C_ARB_ALGORITHM == "ROUND_ROBIN" || C_ARB_ALGORITHM == "FIXED") begin : gen_rr
axis_interconnect_v1_1_arb_rr #(
.C_FAMILY ( C_FAMILY ) ,
.C_NUM_SI_SLOTS ( C_NUM_SI_SLOTS ) ,
.C_LOG_SI_SLOTS ( C_LOG_SI_SLOTS ) ,
.C_ARB_ALGORITHM ( C_ARB_ALGORITHM )
)
arb_rr_0
(
.ACLK ( ACLK ) ,
.ARESET ( areset ) ,
.ACLKEN ( ACLKEN ) ,
.ARB_REQ ( ARB_REQ [i*C_NUM_SI_SLOTS+:C_NUM_SI_SLOTS] ) ,
.ARB_DONE ( ARB_DONE[i] ) ,
.ARB_SEL ( ARB_SEL [i*C_LOG_SI_SLOTS+:C_LOG_SI_SLOTS] ) ,
.ARB_GNT ( ARB_GNT [i*C_NUM_SI_SLOTS+:C_NUM_SI_SLOTS] )
);
end
end
endgenerate
endmodule // axis_switch_arbiter
`default_nettype wire
hdl/platform/artix7/ip_cores/coregen.cgc 0 → 100644
View file @ b5ae2a89
This diff is collapsed.
hdl/platform/artix7/ip_cores/coregen.cgp 0 → 100644
View file @ b5ae2a89
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc7a200t
SET devicefamily = artix7
SET flowvendor = Other
SET package = ffg1156
SET speedgrade = -1
SET verilogsim = false
SET vhdlsim = true
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