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Beam Positoning Monitor - Gateware
Commit b8e77b6e authored by Lucas Russo's avatar Lucas Russo
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modules/*/wb_acq_core/*: calculate coalesce ahead to improve timing

parent 38c15a1d
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Showing with 15 additions and 7 deletions
hdl/modules/dbe_wishbone/wb_acq_core/acq_fsm.vhd
View file @ b8e77b6e
...@@ -174,8 +174,9 @@ architecture rtl of acq_fsm is ...@@ -174,8 +174,9 @@ architecture rtl of acq_fsm is
signal samples_wr_en_d : std_logic; signal samples_wr_en_d : std_logic;
-- Pre/Post trigger and shots counters -- Pre/Post trigger and shots counters
signal curr_num_coalese_log2 : integer := 0; signal curr_num_coalesce_log2 : integer := 0;
signal curr_num_coalese : integer := 0; signal curr_num_coalesce : integer := 0;
signal curr_num_coalesce_minus_1 : t_acq_coalesce;
signal pre_trig_samples_shift_s : std_logic_vector(c_acq_samples_size-1 downto 0); signal pre_trig_samples_shift_s : std_logic_vector(c_acq_samples_size-1 downto 0);
signal post_trig_samples_shift_s : std_logic_vector(c_acq_samples_size-1 downto 0); signal post_trig_samples_shift_s : std_logic_vector(c_acq_samples_size-1 downto 0);
signal pre_trig_samples_shift : unsigned(c_acq_samples_size-1 downto 0); signal pre_trig_samples_shift : unsigned(c_acq_samples_size-1 downto 0);
...@@ -235,10 +236,10 @@ begin ...@@ -235,10 +236,10 @@ begin
-- we need to shift the samples before outputting it to the other -- we need to shift the samples before outputting it to the other
-- logic. This is safe, because the other modules only get this new value -- logic. This is safe, because the other modules only get this new value
-- after lmt_valid signal is asserted -- after lmt_valid signal is asserted
curr_num_coalese_log2 <= c_num_coalesce_log2_array(to_integer(lmt_curr_chan_id_i)); curr_num_coalesce_log2 <= c_num_coalesce_log2_array(to_integer(lmt_curr_chan_id_i));
curr_num_coalese <= c_num_coalesce_array(to_integer(lmt_curr_chan_id_i)); curr_num_coalesce <= c_num_coalesce_array(to_integer(lmt_curr_chan_id_i));
pre_trig_samples_shift_s <= std_logic_vector(shift_left(pre_trig_samples_i, curr_num_coalese_log2)); pre_trig_samples_shift_s <= std_logic_vector(shift_left(pre_trig_samples_i, curr_num_coalesce_log2));
post_trig_samples_shift_s <= std_logic_vector(shift_left(post_trig_samples_i, curr_num_coalese_log2)); post_trig_samples_shift_s <= std_logic_vector(shift_left(post_trig_samples_i, curr_num_coalesce_log2));
pre_trig_samples_shift <= unsigned(pre_trig_samples_shift_s); pre_trig_samples_shift <= unsigned(pre_trig_samples_shift_s);
post_trig_samples_shift <= unsigned(post_trig_samples_shift_s); post_trig_samples_shift <= unsigned(post_trig_samples_shift_s);
...@@ -492,6 +493,9 @@ begin ...@@ -492,6 +493,9 @@ begin
if fs_rst_n = '0' then if fs_rst_n = '0' then
acq_fsm_current_state := IDLE; acq_fsm_current_state := IDLE;
-- Intermediate results for better timing
curr_num_coalesce_minus_1 <= to_unsigned(0, curr_num_coalesce_minus_1'length);
-- Outputs -- Outputs
shots_decr <= '0'; shots_decr <= '0';
acq_in_pre_trig <= '0'; acq_in_pre_trig <= '0';
...@@ -521,6 +525,10 @@ begin ...@@ -521,6 +525,10 @@ begin
wait_trig_skip_done_ext <= '0'; wait_trig_skip_done_ext <= '0';
post_trig_done_ext <= '0'; post_trig_done_ext <= '0';
-- Intermediate results for better timing
curr_num_coalesce_minus_1 <= to_unsigned(curr_num_coalesce,
curr_num_coalesce_minus_1'length)-1;
-- FSM transitions -- FSM transitions
case acq_fsm_current_state is case acq_fsm_current_state is
...@@ -533,7 +541,7 @@ begin ...@@ -533,7 +541,7 @@ begin
-- Only at the start of the acquisition, wait until we are -- Only at the start of the acquisition, wait until we are
-- at the beginning of the atom word. This will assure us that -- at the beginning of the atom word. This will assure us that
-- we are acquiring the complete word, at all times. -- we are acquiring the complete word, at all times.
if acq_id_i = curr_num_coalese-1 and acq_dvalid_i = '1' then if acq_id_i = curr_num_coalesce_minus_1 and acq_dvalid_i = '1' then
acq_fsm_current_state := PRE_TRIG; acq_fsm_current_state := PRE_TRIG;
end if; end if;
......
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