Skip to content

B
Beam Positoning Monitor - Gateware
Commit b994da8a authored by Lucas Russo's avatar Lucas Russo
Browse files
Options

wb_fmc516/*: add wishbone register interface

parent 5b4ca93c
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 6917 additions and 884 deletions
hdl/modules/custom_wishbone/wb_fmc516/Manifest.py
View file @ b994da8a
files = [ "wb_fmc516.vhd", "fmc516_adc_clk.vhd",
"fmc516_adc_data.vhd", "fmc516_adc_iface.vhd"
"fmc516_adc_data.vhd", "fmc516_adc_iface.vhd",
"xfmc516_regs_pkg.vhd", "wb_fmc516_port.vhd"
# "xwb_fmc516.vhd",
# "wb_fmc516.ucf"
];
hdl/modules/custom_wishbone/wb_fmc516/doc/xfmc516_regs_wb.html 0 → 100644
View file @ b994da8a
This diff is collapsed.
hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.h 0 → 100644
View file @ b994da8a
This diff is collapsed.
hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516_port.vhd 0 → 100644
View file @ b994da8a
This diff is collapsed.
hdl/modules/custom_wishbone/wb_fmc516/xfmc516_regs_pkg.vhd 0 → 100644
View file @ b994da8a
This diff is collapsed.
hdl/sim/regs/xfmc516_regs.vh 0 → 100644
View file @ b994da8a
`define ADDR_FMC516_FMC_CTL 6'h0
`define FMC516_FMC_CTL_TEST_DATA_EN_OFFSET 0
`define FMC516_FMC_CTL_TEST_DATA_EN 32'h00000001
`define FMC516_FMC_CTL_LED_0_OFFSET 1
`define FMC516_FMC_CTL_LED_0 32'h00000002
`define FMC516_FMC_CTL_LED_1_OFFSET 2
`define FMC516_FMC_CTL_LED_1 32'h00000004
`define FMC516_FMC_CTL_RESERVED_OFFSET 3
`define FMC516_FMC_CTL_RESERVED 32'hfffffff8
`define ADDR_FMC516_FMC_STA 6'h4
`define FMC516_FMC_STA_MMCM_LOCKED_OFFSET 0
`define FMC516_FMC_STA_MMCM_LOCKED 32'h00000001
`define FMC516_FMC_STA_PWR_GOOD_OFFSET 1
`define FMC516_FMC_STA_PWR_GOOD 32'h00000002
`define FMC516_FMC_STA_PRST_OFFSET 2
`define FMC516_FMC_STA_PRST 32'h00000004
`define FMC516_FMC_STA_RESERVED_OFFSET 3
`define FMC516_FMC_STA_RESERVED 32'hfffffff8
`define ADDR_FMC516_TRIG_CFG 6'h8
`define FMC516_TRIG_CFG_HW_TRIG_POL_OFFSET 0
`define FMC516_TRIG_CFG_HW_TRIG_POL 32'h00000001
`define FMC516_TRIG_CFG_HW_TRIG_EN_OFFSET 1
`define FMC516_TRIG_CFG_HW_TRIG_EN 32'h00000002
`define FMC516_TRIG_CFG_RESERVED_OFFSET 2
`define FMC516_TRIG_CFG_RESERVED 32'hfffffffc
`define ADDR_FMC516_ADC_STA 6'hc
`define FMC516_ADC_STA_CLK_CHAINS_OFFSET 0
`define FMC516_ADC_STA_CLK_CHAINS 32'h0000000f
`define FMC516_ADC_STA_DATA_CHAINS_OFFSET 8
`define FMC516_ADC_STA_DATA_CHAINS 32'h00000f00
`define FMC516_ADC_STA_ADC_PKT_SIZE_OFFSET 16
`define FMC516_ADC_STA_ADC_PKT_SIZE 32'hffff0000
`define ADDR_FMC516_ADC_CTL 6'h10
`define FMC516_ADC_CTL_UPDATE_DLY_OFFSET 0
`define FMC516_ADC_CTL_UPDATE_DLY 32'h00000001
`define FMC516_ADC_CTL_RESERVED_OFFSET 1
`define FMC516_ADC_CTL_RESERVED 32'hfffffffe
`define ADDR_FMC516_CH0_STA 6'h14
`define FMC516_CH0_STA_VAL_OFFSET 0
`define FMC516_CH0_STA_VAL 32'h0000ffff
`define FMC516_CH0_STA_RESERVED_OFFSET 16
`define FMC516_CH0_STA_RESERVED 32'hffff0000
`define ADDR_FMC516_CH0_CTL 6'h18
`define FMC516_CH0_CTL_CLK_CHAIN_DLY_OFFSET 0
`define FMC516_CH0_CTL_CLK_CHAIN_DLY 32'h0000001f
`define FMC516_CH0_CTL_DATA_CHAIN_DLY_OFFSET 8
`define FMC516_CH0_CTL_DATA_CHAIN_DLY 32'h00001f00
`define FMC516_CH0_CTL_RESERVED_OFFSET 16
`define FMC516_CH0_CTL_RESERVED 32'hffff0000
`define ADDR_FMC516_CH1_STA 6'h1c
`define FMC516_CH1_STA_VAL_OFFSET 0
`define FMC516_CH1_STA_VAL 32'h0000ffff
`define FMC516_CH1_STA_RESERVED_OFFSET 16
`define FMC516_CH1_STA_RESERVED 32'hffff0000
`define ADDR_FMC516_CH1_CTL 6'h20
`define FMC516_CH1_CTL_CLK_CHAIN_DLY_OFFSET 0
`define FMC516_CH1_CTL_CLK_CHAIN_DLY 32'h0000001f
`define FMC516_CH1_CTL_DATA_CHAIN_DLY_OFFSET 8
`define FMC516_CH1_CTL_DATA_CHAIN_DLY 32'h00001f00
`define FMC516_CH1_CTL_RESERVED_OFFSET 16
`define FMC516_CH1_CTL_RESERVED 32'hffff0000
`define ADDR_FMC516_CH2_STA 6'h24
`define FMC516_CH2_STA_VAL_OFFSET 0
`define FMC516_CH2_STA_VAL 32'h0000ffff
`define FMC516_CH2_STA_RESERVED_OFFSET 16
`define FMC516_CH2_STA_RESERVED 32'hffff0000
`define ADDR_FMC516_CH2_CTL 6'h28
`define FMC516_CH2_CTL_CLK_CHAIN_DLY_OFFSET 0
`define FMC516_CH2_CTL_CLK_CHAIN_DLY 32'h0000001f
`define FMC516_CH2_CTL_DATA_CHAIN_DLY_OFFSET 8
`define FMC516_CH2_CTL_DATA_CHAIN_DLY 32'h00001f00
`define FMC516_CH2_CTL_RESERVED_OFFSET 16
`define FMC516_CH2_CTL_RESERVED 32'hffff0000
`define ADDR_FMC516_CH3_STA 6'h2c
`define FMC516_CH3_STA_VAL_OFFSET 0
`define FMC516_CH3_STA_VAL 32'h0000ffff
`define FMC516_CH3_STA_RESERVED_OFFSET 16
`define FMC516_CH3_STA_RESERVED 32'hffff0000
`define ADDR_FMC516_CH3_CTL 6'h30
`define FMC516_CH3_CTL_CLK_CHAIN_DLY_OFFSET 0
`define FMC516_CH3_CTL_CLK_CHAIN_DLY 32'h0000001f
`define FMC516_CH3_CTL_DATA_CHAIN_DLY_OFFSET 8
`define FMC516_CH3_CTL_DATA_CHAIN_DLY 32'h00001f00
`define FMC516_CH3_CTL_RESERVED_OFFSET 16
`define FMC516_CH3_CTL_RESERVED 32'hffff0000
hdl/syn/dbe_bpm_simple/dbe_bpm_simple.gise
View file @ b994da8a
......@@ -62,6 +62,7 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="dbe_bpm_simple_top_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="dbe_bpm_simple_top_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="dbe_bpm_simple_top_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="dbe_bpm_simple_top_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="dbe_bpm_simple_top_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="dbe_bpm_simple_top_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="dbe_bpm_simple_top_xst.xrpt"/>
......@@ -100,21 +101,15 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1351103103" xil_pn:in_ck="-3676352999506393327" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="4204764714131478187" xil_pn:start_ts="1351102968">
<status xil_pn:value="SuccessfullyRun"/>
<transform xil_pn:end_ts="1352742642" xil_pn:in_ck="-3676352999506393327" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="4204764714131478187" xil_pn:start_ts="1352742618">
<status xil_pn:value="AbortedRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="dbe_bpm_simple_top.lso"/>
<outfile xil_pn:name="dbe_bpm_simple_top.ngc"/>
<outfile xil_pn:name="dbe_bpm_simple_top.ngr"/>
<outfile xil_pn:name="dbe_bpm_simple_top.prj"/>
<outfile xil_pn:name="dbe_bpm_simple_top.stx"/>
<outfile xil_pn:name="dbe_bpm_simple_top.syr"/>
<outfile xil_pn:name="dbe_bpm_simple_top.xst"/>
<outfile xil_pn:name="dbe_bpm_simple_top_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
......@@ -125,57 +120,48 @@
<transform xil_pn:end_ts="1351103130" xil_pn:in_ck="4181690111764201426" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-8990626865624946785" xil_pn:start_ts="1351103103">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="dbe_bpm_simple_top.bld"/>
<outfile xil_pn:name="dbe_bpm_simple_top.ngd"/>
<outfile xil_pn:name="dbe_bpm_simple_top_ngdbuild.xrpt"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1351103287" xil_pn:in_ck="-956280685729320234" xil_pn:name="TRANEXT_map_virtex6" xil_pn:prop_ck="5939692501008836605" xil_pn:start_ts="1351103130">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="dbe_bpm_simple_top.pcf"/>
<outfile xil_pn:name="dbe_bpm_simple_top_map.map"/>
<outfile xil_pn:name="dbe_bpm_simple_top_map.mrp"/>
<outfile xil_pn:name="dbe_bpm_simple_top_map.ncd"/>
<outfile xil_pn:name="dbe_bpm_simple_top_map.ngm"/>
<outfile xil_pn:name="dbe_bpm_simple_top_map.xrpt"/>
<outfile xil_pn:name="dbe_bpm_simple_top_summary.xml"/>
<outfile xil_pn:name="dbe_bpm_simple_top_usage.xml"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1351103443" xil_pn:in_ck="-4414935198573544209" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="6734387949470617483" xil_pn:start_ts="1351103287">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="dbe_bpm_simple_top.ncd"/>
<outfile xil_pn:name="dbe_bpm_simple_top.pad"/>
<outfile xil_pn:name="dbe_bpm_simple_top.par"/>
<outfile xil_pn:name="dbe_bpm_simple_top.ptwx"/>
<outfile xil_pn:name="dbe_bpm_simple_top.unroutes"/>
<outfile xil_pn:name="dbe_bpm_simple_top.xpi"/>
<outfile xil_pn:name="dbe_bpm_simple_top_pad.csv"/>
<outfile xil_pn:name="dbe_bpm_simple_top_pad.txt"/>
<outfile xil_pn:name="dbe_bpm_simple_top_par.xrpt"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1351103573" xil_pn:in_ck="1577483878535902759" xil_pn:name="TRANEXT_bitFile_virtex6" xil_pn:prop_ck="8799862395714727328" xil_pn:start_ts="1351103443">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="AbortedRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="dbe_bpm_simple_top.bgn"/>
<outfile xil_pn:name="dbe_bpm_simple_top.bit"/>
<outfile xil_pn:name="dbe_bpm_simple_top.drc"/>
<outfile xil_pn:name="dbe_bpm_simple_top.ut"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1351103443" xil_pn:in_ck="-956280685729320366" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416183" xil_pn:start_ts="1351103412">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="dbe_bpm_simple_top.twr"/>
<outfile xil_pn:name="dbe_bpm_simple_top.twx"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
</transforms>
......
hdl/syn/dbe_bpm_simple/dbe_bpm_simple.xise
View file @ b994da8a
......@@ -101,6 +101,7 @@
<property xil_pn:name="Equivalent Register Removal" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
......@@ -158,6 +159,9 @@
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -217,6 +221,7 @@
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment