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Beam Positoning Monitor - Gateware
Commit cc7b7d2b authored by Lucas Russo's avatar Lucas Russo
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modules/*: add new FMC Pico 1M_4CH module 

Warning! This is still missing the actual
FMC SPI acquisition.
parent f5455bf8
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hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/Manifest.py 0 → 100644
View file @ cc7b7d2b
files = [
"cdc_fifo.vhd",
"fmc_pico_spi.v",
"wb_fmcpico1m_4ch.vhd",
"xwb_fmcpico1m_4ch.vhd",
"wbgen/fmc_pico1m_4ch_regs_pkg.vhd",
"wbgen/fmc_pico1m_4ch_regs.vhd"
];
hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/cdc_fifo.vhd 0 → 100644
View file @ cc7b7d2b
------------------------------------------------------------------------------
-- Title : CDC FIFO for Position data
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-09-23
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: CDC FIFO for generic data. Suitable for CDC position data
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-09-23 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Genrams
use work.genram_pkg.all;
use work.dsp_cores_pkg.all;
entity cdc_fifo is
generic
(
g_data_width : natural;
g_size : natural
);
port
(
clk_wr_i : in std_logic;
data_i : in std_logic_vector(g_data_width-1 downto 0);
valid_i : in std_logic;
clk_rd_i : in std_logic;
data_o : out std_logic_vector(g_data_width-1 downto 0);
valid_o : out std_logic
);
end cdc_fifo;
architecture rtl of cdc_fifo is
constant c_guard_size : integer := 2;
constant c_almost_empty_thres : integer := c_guard_size;
constant c_almost_full_thres : integer := g_size - c_guard_size;
signal fifo_cdc_rd : std_logic;
signal fifo_cdc_empty : std_logic;
signal fifo_cdc_valid : std_logic;
begin
cmp_cdc_fifo : inferred_async_fifo
generic map(
g_data_width => g_data_width,
g_size => g_size,
g_almost_empty_threshold => c_almost_empty_thres,
g_almost_full_threshold => c_almost_full_thres
)
port map(
rst_n_i => '1',
-- write port
clk_wr_i => clk_wr_i,
d_i => data_i,
we_i => valid_i, -- and valid
wr_full_o => open,
-- read port
clk_rd_i => clk_rd_i,
q_o => data_o,
rd_i => fifo_cdc_rd,
rd_empty_o => fifo_cdc_empty
);
fifo_cdc_rd <= '1' when fifo_cdc_empty = '0' else '0';
p_gen_cdc_valid: process (clk_rd_i)
begin
if rising_edge (clk_rd_i) then
fifo_cdc_valid <= fifo_cdc_rd;
if fifo_cdc_empty = '1' then
fifo_cdc_valid <= '0';
end if;
end if;
end process;
valid_o <= fifo_cdc_valid;
end rtl;
hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wb_fmcpico1m_4ch.vhd 0 → 100644
View file @ cc7b7d2b
This diff is collapsed.
hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/build_wb.sh 0 → 100755
View file @ cc7b7d2b
#!/bin/bash
wbgen2 -V fmc_pico1m_4ch_regs.vhd -H record -p fmc_pico1m_4ch_regs_pkg.vhd -K ../../../../sim/regs/wb_fmcpico1m_4ch_regs.vh -s defines -C fmcpico1m_4ch_regs.h -f html -D doc/fmcpico1m_4ch_regs_wb.html fmc_pico1m_4ch_regs.wb
hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/fmc_pico1m_4ch_regs.wb 0 → 100644
View file @ cc7b7d2b
peripheral {
name = "Control and status registers for FMC PICO 1M 4CH";
description = "Wishbone slave for control and status registers related to FMC PICO 1M 4CH with access from CSR bus";
hdl_entity = "wb_fmc_pico1m_4ch_csr";
prefix = "wb_fmc_pico1m_4ch_csr";
reg {
name = "FMC Status";
prefix = "fmc_status";
field {
name = "FMC Present";
prefix = "prsnt";
description = "FMC PRSNT_M2C Pin\n0 - FMC card present\n1 - no FMC card on carrier";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Power Good from mezzanine";
prefix = "pg_m2c";
description = "FMC Power Good Pin\nNot used";
type = BIT;
--size = 1;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "FMC Control";
prefix = "fmc_ctl";
field {
name = "LED 1 Control";
prefix = "led1";
description = "0 - Led Off\n1 - Led On";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "LED 2 Control";
prefix = "led2";
description = "0 - Led Off\n1 - Led On";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Input Range Control";
prefix = "rng_ctl";
field {
name = "R0";
prefix = "r0";
description = "Input Range Control for ADC0\n0 - RNG1 = +/- 1uA\n1 - RNG0 = +/- 1mA";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "R1";
prefix = "r1";
description = "Input Range Control for ADC1\n0 - RNG1 = +/- 1uA\n1 - RNG0 = +/- 1mA";
align = 8;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "R2";
prefix = "r2";
description = "Input Range Control for ADC2\n0 - RNG1 = +/- 1uA\n1 - RNG0 = +/- 1mA";
align = 16;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "R3";
prefix = "r3";
description = "Input Range Control for ADC3\n0 - RNG1 = +/- 1uA\n1 - RNG0 = +/- 1mA";
align = 24;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "ADC Data Channel 0";
prefix = "data0";
field {
name = "DATA0";
prefix = "val";
description = "ADC data from channel 0";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "ADC Data Channel 1";
prefix = "data1";
field {
name = "DATA1";
prefix = "val";
description = "ADC data from channel 1";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "ADC Data Channel 2";
prefix = "data2";
field {
name = "DATA2";
prefix = "val";
description = "ADC data from channel 2";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "ADC Data Channel 3";
prefix = "data3";
field {
name = "DATA3";
prefix = "val";
description = "ADC data from channel 3";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/fmc_pico1m_4ch_regs_pkg.vhd 0 → 100644
View file @ cc7b7d2b
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Control and status registers for FMC PICO 1M 4CH
---------------------------------------------------------------------------------------
-- File : fmc_pico1m_4ch_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from fmc_pico1m_4ch_regs.wb
-- Created : Tue Dec 8 15:27:17 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_pico1m_4ch_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wb_fmc_pico1m_4ch_csr_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_wb_fmc_pico1m_4ch_csr_in_registers is record
fmc_status_prsnt_i : std_logic;
fmc_status_pg_m2c_i : std_logic;
data0_val_i : std_logic_vector(31 downto 0);
data1_val_i : std_logic_vector(31 downto 0);
data2_val_i : std_logic_vector(31 downto 0);
data3_val_i : std_logic_vector(31 downto 0);
end record;
constant c_wb_fmc_pico1m_4ch_csr_in_registers_init_value: t_wb_fmc_pico1m_4ch_csr_in_registers := (
fmc_status_prsnt_i => '0',
fmc_status_pg_m2c_i => '0',
data0_val_i => (others => '0'),
data1_val_i => (others => '0'),
data2_val_i => (others => '0'),
data3_val_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_wb_fmc_pico1m_4ch_csr_out_registers is record
fmc_ctl_led1_o : std_logic;
fmc_ctl_led2_o : std_logic;
rng_ctl_r0_o : std_logic;
rng_ctl_r1_o : std_logic;
rng_ctl_r2_o : std_logic;
rng_ctl_r3_o : std_logic;
end record;
constant c_wb_fmc_pico1m_4ch_csr_out_registers_init_value: t_wb_fmc_pico1m_4ch_csr_out_registers := (
fmc_ctl_led1_o => '0',
fmc_ctl_led2_o => '0',
rng_ctl_r0_o => '0',
rng_ctl_r1_o => '0',
rng_ctl_r2_o => '0',
rng_ctl_r3_o => '0'
);
function "or" (left, right: t_wb_fmc_pico1m_4ch_csr_in_registers) return t_wb_fmc_pico1m_4ch_csr_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body wb_fmc_pico1m_4ch_csr_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_wb_fmc_pico1m_4ch_csr_in_registers) return t_wb_fmc_pico1m_4ch_csr_in_registers is
variable tmp: t_wb_fmc_pico1m_4ch_csr_in_registers;
begin
tmp.fmc_status_prsnt_i := f_x_to_zero(left.fmc_status_prsnt_i) or f_x_to_zero(right.fmc_status_prsnt_i);
tmp.fmc_status_pg_m2c_i := f_x_to_zero(left.fmc_status_pg_m2c_i) or f_x_to_zero(right.fmc_status_pg_m2c_i);
tmp.data0_val_i := f_x_to_zero(left.data0_val_i) or f_x_to_zero(right.data0_val_i);
tmp.data1_val_i := f_x_to_zero(left.data1_val_i) or f_x_to_zero(right.data1_val_i);
tmp.data2_val_i := f_x_to_zero(left.data2_val_i) or f_x_to_zero(right.data2_val_i);
tmp.data3_val_i := f_x_to_zero(left.data3_val_i) or f_x_to_zero(right.data3_val_i);
return tmp;
end function;
end package body;
hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/fmcpico1m_4ch_regs.h 0 → 100644
View file @ cc7b7d2b
/*
Register definitions for slave core: Control and status registers for FMC PICO 1M 4CH
* File : fmcpico1m_4ch_regs.h
* Author : auto-generated by wbgen2 from fmc_pico1m_4ch_regs.wb
* Created : Tue Dec 8 15:27:17 2015
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_pico1m_4ch_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_FMC_PICO1M_4CH_REGS_WB
#define __WBGEN2_REGDEFS_FMC_PICO1M_4CH_REGS_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: FMC Status */
/* definitions for field: FMC Present in reg: FMC Status */
#define WB_FMC_PICO1M_4CH_CSR_FMC_STATUS_PRSNT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Power Good from mezzanine in reg: FMC Status */
#define WB_FMC_PICO1M_4CH_CSR_FMC_STATUS_PG_M2C WBGEN2_GEN_MASK(1, 1)
/* definitions for register: FMC Control */
/* definitions for field: LED 1 Control in reg: FMC Control */
#define WB_FMC_PICO1M_4CH_CSR_FMC_CTL_LED1 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: LED 2 Control in reg: FMC Control */
#define WB_FMC_PICO1M_4CH_CSR_FMC_CTL_LED2 WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Input Range Control */
/* definitions for field: R0 in reg: Input Range Control */
#define WB_FMC_PICO1M_4CH_CSR_RNG_CTL_R0 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: R1 in reg: Input Range Control */
#define WB_FMC_PICO1M_4CH_CSR_RNG_CTL_R1 WBGEN2_GEN_MASK(8, 1)
/* definitions for field: R2 in reg: Input Range Control */
#define WB_FMC_PICO1M_4CH_CSR_RNG_CTL_R2 WBGEN2_GEN_MASK(16, 1)
/* definitions for field: R3 in reg: Input Range Control */
#define WB_FMC_PICO1M_4CH_CSR_RNG_CTL_R3 WBGEN2_GEN_MASK(24, 1)
/* definitions for register: ADC Data Channel 0 */
/* definitions for field: DATA0 in reg: ADC Data Channel 0 */
#define WB_FMC_PICO1M_4CH_CSR_DATA0_VAL_MASK WBGEN2_GEN_MASK(0, 32)
#define WB_FMC_PICO1M_4CH_CSR_DATA0_VAL_SHIFT 0
#define WB_FMC_PICO1M_4CH_CSR_DATA0_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WB_FMC_PICO1M_4CH_CSR_DATA0_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: ADC Data Channel 1 */
/* definitions for field: DATA1 in reg: ADC Data Channel 1 */
#define WB_FMC_PICO1M_4CH_CSR_DATA1_VAL_MASK WBGEN2_GEN_MASK(0, 32)
#define WB_FMC_PICO1M_4CH_CSR_DATA1_VAL_SHIFT 0
#define WB_FMC_PICO1M_4CH_CSR_DATA1_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WB_FMC_PICO1M_4CH_CSR_DATA1_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: ADC Data Channel 2 */
/* definitions for field: DATA2 in reg: ADC Data Channel 2 */
#define WB_FMC_PICO1M_4CH_CSR_DATA2_VAL_MASK WBGEN2_GEN_MASK(0, 32)
#define WB_FMC_PICO1M_4CH_CSR_DATA2_VAL_SHIFT 0
#define WB_FMC_PICO1M_4CH_CSR_DATA2_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WB_FMC_PICO1M_4CH_CSR_DATA2_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: ADC Data Channel 3 */
/* definitions for field: DATA3 in reg: ADC Data Channel 3 */
#define WB_FMC_PICO1M_4CH_CSR_DATA3_VAL_MASK WBGEN2_GEN_MASK(0, 32)
#define WB_FMC_PICO1M_4CH_CSR_DATA3_VAL_SHIFT 0
#define WB_FMC_PICO1M_4CH_CSR_DATA3_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WB_FMC_PICO1M_4CH_CSR_DATA3_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* [0x0]: REG FMC Status */
#define WB_FMC_PICO1M_4CH_CSR_REG_FMC_STATUS 0x00000000
/* [0x4]: REG FMC Control */
#define WB_FMC_PICO1M_4CH_CSR_REG_FMC_CTL 0x00000004
/* [0x8]: REG Input Range Control */
#define WB_FMC_PICO1M_4CH_CSR_REG_RNG_CTL 0x00000008
/* [0xc]: REG ADC Data Channel 0 */
#define WB_FMC_PICO1M_4CH_CSR_REG_DATA0 0x0000000c
/* [0x10]: REG ADC Data Channel 1 */
#define WB_FMC_PICO1M_4CH_CSR_REG_DATA1 0x00000010
/* [0x14]: REG ADC Data Channel 2 */
#define WB_FMC_PICO1M_4CH_CSR_REG_DATA2 0x00000014
/* [0x18]: REG ADC Data Channel 3 */
#define WB_FMC_PICO1M_4CH_CSR_REG_DATA3 0x00000018
#endif
hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/xwb_fmcpico1m_4ch.vhd 0 → 100644
View file @ cc7b7d2b
------------------------------------------------------------------------------
-- Title : Wishbone FMC250 Interface
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2016-02-19
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Top Module for the BPM with FMC250.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-02-19 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Wishbone Stream Interface
use work.wb_stream_generic_pkg.all;
-- FMC ADC package
--use work.fmc_adc_pkg.all;
entity xwb_fmcpico1m_4ch is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_adc_bits : natural := 20;
g_num_adc_channels : natural := 4;
g_clk_freq : natural := 300000000; -- Hz
g_sclk_freq : natural := 75000000 --Hz
);
port
(
sys_clk_i : in std_logic;
sys_rst_n_i : in std_logic;
sys_clk_200Mhz_i : in std_logic;
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
adc_fast_spi_clk_i : in std_logic;
adc_fast_spi_rstn_i : in std_logic;
-- Control signals
adc_start_i : in std_logic;
-- SPI bus
adc_sdo1_i : in std_logic;
adc_sdo2_i : in std_logic;
adc_sdo3_i : in std_logic;
adc_sdo4_i : in std_logic;
adc_sck_o : out std_logic;
adc_sck_rtrn_i : in std_logic;
adc_busy_cmn_i : in std_logic;
adc_cnv_out_o : out std_logic;
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
-- clock to CDC. This must be g_sclk_freq/g_num_adc_bits. A regular 100MHz should
-- suffice in all cases
adc_clk_i : in std_logic;
adc_data_o : out std_logic_vector(g_num_adc_channels*g_num_adc_bits-1 downto 0);
adc_data_valid_o : out std_logic_vector(g_num_adc_channels-1 downto 0);
adc_out_busy_o : out std_logic
);
end xwb_fmcpico1m_4ch;
architecture rtl of xwb_fmcpico1m_4ch is
signal wbs_adr_int : std_logic_vector(c_num_adc_channels*c_wbs_adr4_width-1 downto 0);
signal wbs_dat_int : std_logic_vector(c_num_adc_channels*c_wbs_dat16_width-1 downto 0);
signal wbs_cyc_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal wbs_stb_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal wbs_we_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal wbs_sel_int : std_logic_vector(c_num_adc_channels*c_wbs_sel16_width-1 downto 0);
signal wbs_ack_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal wbs_stall_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal wbs_err_int : std_logic_vector(c_num_adc_channels-1 downto 0);
signal wbs_rty_int : std_logic_vector(c_num_adc_channels-1 downto 0);
begin
cmp_wb_fmcpico1m_4ch : wb_fmcpico1m_4ch
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_num_adc_bits => g_num_adc_bits,
g_num_adc_channels => g_num_adc_channels,
g_clk_freq => g_clk_freq,
g_sclk_freq => g_sclk_freq
)
port map (
sys_clk_i => sys_clk_i,
sys_rst_n_i => sys_rst_n_i,
sys_clk_200Mhz_i => sys_clk_200Mhz_i,
-----------------------------
-- Wishbone Control Interface signals
-----------------------------
wb_adr_i => wb_slv_i.adr,
wb_dat_i => wb_slv_i.dat,
wb_dat_o => wb_slv_o.dat,
wb_sel_i => wb_slv_i.sel,
wb_we_i => wb_slv_i.we,
wb_cyc_i => wb_slv_i.cyc,
wb_stb_i => wb_slv_i.stb,
wb_ack_o => wb_slv_o.ack,
wb_err_o => wb_slv_o.err,
wb_rty_o => wb_slv_o.rty,
wb_stall_o => wb_slv_o.stall,
-----------------------------
-- External ports
-----------------------------
adc_fast_spi_clk_i => adc_fast_spi_clk_i,
adc_fast_spi_rstn_i => adc_fast_spi_rstn_i,
-- Control signals
adc_start_i => adc_start_i,
-- SPI bus
adc_sdo1_i => adc_sdo1_i,
adc_sdo2_i => adc_sdo2_i,
adc_sdo3_i => adc_sdo3_i,
adc_sdo4_i => adc_sdo4_i,
adc_sck_o => adc_sck_o,
adc_sck_rtrn_i => adc_sck_rtrn_i,
adc_busy_cmn_i => adc_busy_cmn_i,
adc_cnv_out_o => adc_cnv_out_o,
-----------------------------
-- ADC output signals. Continuous flow
-----------------------------
-- clock to CDC. This must be g_sclk_freq/g_num_adc_bits. A regular 100MHz should
-- suffice in all cases
adc_clk_i => adc_clk_i,
adc_data_o => adc_data_o,
adc_data_valid_o => adc_data_valid_o,
adc_out_busy_o => adc_out_busy_o
);
--gen_wbs_interfaces : for i in 0 to c_num_adc_channels-1 generate
-- gen_wbs_interfaces_ch : if g_use_data_chains(i) = '1' generate
-- wbs_ack_int(i) <= wbs_source_i(i).ack;
-- wbs_stall_int(i) <= wbs_source_i(i).stall;
-- wbs_err_int(i) <= wbs_source_i(i).err;
-- wbs_rty_int(i) <= wbs_source_i(i).rty;
-- wbs_source_o(i).adr <= wbs_adr_int(c_wbs_adr4_width*(i+1)-1 downto
-- c_wbs_adr4_width*i);
-- wbs_source_o(i).dat <= wbs_dat_int(c_wbs_dat16_width*(i+1)-1 downto
-- c_wbs_dat16_width*i);
-- wbs_source_o(i).sel <= wbs_sel_int(c_wbs_sel16_width*(i+1)-1 downto
-- c_wbs_sel16_width*i);
-- wbs_source_o(i).cyc <= wbs_cyc_int(i);
-- wbs_source_o(i).stb <= wbs_stb_int(i);
-- wbs_source_o(i).we <= wbs_we_int(i);
-- end generate;
--end generate;
end rtl;
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