hdl/top/top/afc_v1/*: add divclk generic to PLL

This allow us to select a broader range of frequencies, in order to generate a 100 MHz clock from a 125 MHz clock source, for instance

hdl/top/top/afc_v1/*: add divclk generic to PLL
This allow us to select a broader range of frequencies, in order to generate a 100 MHz clock from a 125 MHz clock source, for instance
d13d99a7 · Lucas Russo · 0db949eb · d13d99a7 · d13d99a7
Commit d13d99a7 authored Jun 02, 2014 by Lucas Russo
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Showing with 13 additions and 3 deletions

dbe_bpm_dsp.vhd hdl/top/afc_v1/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd +11 -1

sys_pll.vhd hdl/top/afc_v1/dbe_bpm_dsp_fmc130m_4ch/sys_pll.vhd +2 -2

No files found.
--- a/hdl/top/afc_v1/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd
+++ b/hdl/top/afc_v1/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd
@@ -1193,6 +1193,17 @@ begin

  -- Obtain core locking and generate necessary clocks
  cmp_sys_pll_inst : sys_pll
+  generic map (
+    -- 125 MHz input clock
+    g_clkin_period                          => 8.000,
+    g_divclk_divide                         => 5,
+    g_clkbout_mult_f                        => 32,
+                                         
+    -- 100 MHz output clock          
+    g_clk0_divide_f                         => 8.000,
+    -- 200 MHz output clock     
+    g_clk1_divide                           => 4
+  )    
  port map (
    rst_i                                   => '0',
    clk_i                                   => sys_clk_gen_bufg,
@@ -2959,4 +2970,3 @@ begin
  --);

 end ;
-
--- a/hdl/top/afc_v1/dbe_bpm_dsp_fmc130m_4ch/sys_pll.vhd
+++ b/hdl/top/afc_v1/dbe_bpm_dsp_fmc130m_4ch/sys_pll.vhd
@@ -27,6 +27,7 @@ entity sys_pll is
 generic(
  -- 200 MHz input clock
  g_clkin_period                            : real := 5.000;
+  g_divclk_divide                           : integer := 1;
  g_clkbout_mult_f                          : real := 5.000;
        
  -- 100 MHz output clock             
@@ -64,7 +65,7 @@ begin
    CLOCK_HOLD                              => FALSE,
    COMPENSATION                            => "ZHOLD",
    STARTUP_WAIT                            => FALSE,
-    DIVCLK_DIVIDE                           => 1,
+    DIVCLK_DIVIDE                           => g_divclk_divide,
    CLKFBOUT_MULT_F                         => g_clkbout_mult_f,
    CLKFBOUT_PHASE                          => 0.000,
    CLKFBOUT_USE_FINE_PS                    => FALSE,
@@ -146,4 +147,3 @@ begin
    );

 end syn;
-