hdl/modules/dbe_common/*: add pulse2level component

Added module for converting a one clock tick pulse into a level. Clear signal providfing for reseting the level to 0. For now, it only detects a positive-edge pulse.

hdl/modules/dbe_common/*: add pulse2level component
Added module for converting a one clock tick pulse into a level. Clear signal providfing for reseting the level to 0. For now, it only detects a positive-edge pulse.
dcc348b2 · Lucas Russo · f3d4ffd5 · dcc348b2 · dcc348b2 · dcc348b2
Commit dcc348b2 authored Sep 16, 2014 by Lucas Russo
4 changed files
--- a/hdl/modules/dbe_common/Manifest.py
+++ b/hdl/modules/dbe_common/Manifest.py
-modules = { "local" : ["reset_synch"] };
+modules = { "local" : ["reset_synch",
+                        "pulse2level"] };

 files = [ "dbe_common_pkg.vhd" ];
--- a/hdl/modules/dbe_common/dbe_common_pkg.vhd
+++ b/hdl/modules/dbe_common/dbe_common_pkg.vhd
@@ -6,6 +6,7 @@ package dbe_common_pkg is
  --------------------------------------------------------------------
  -- Components
  --------------------------------------------------------------------
+
  component reset_synch
  generic
  (
@@ -21,4 +22,19 @@ package dbe_common_pkg is
  );
  end component;

+  component pulse2level
+  port
+  (
+    clk_i                                  : in std_logic;
+    rst_n_i                                : in std_logic;
+
+    -- Pulse input
+    pulse_i                                : in std_logic;
+    -- Clear level
+    clr_i                                  : in std_logic;
+    -- Level output
+    level_o                                : out std_logic
+  );
+  end component;
+
 end dbe_common_pkg;
--- a/hdl/modules/dbe_common/pulse2level/Manifest.py
+++ b/hdl/modules/dbe_common/pulse2level/Manifest.py
+files = [ "pulse2level.vhd" ];
--- a/hdl/modules/dbe_common/pulse2level/pulse2level.vhd
+++ b/hdl/modules/dbe_common/pulse2level/pulse2level.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity pulse2level is
+port
+(
+  clk_i                                    : in std_logic;
+  rst_n_i                                  : in std_logic;
+
+  -- Pulse input
+  pulse_i                                  : in std_logic;
+  -- Clear level
+  clr_i                                    : in std_logic;
+  -- Level output
+  level_o                                  : out std_logic
+);
+end pulse2level;
+
+architecture rtl of pulse2level is
+  signal level                             : std_logic := '0';
+begin
+
+  -- Convert from pulse to level signal
+  p_pulse_to_level : process (clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        level <= '0';
+      else
+        if clr_i = '1'then
+          level <= '0';
+        elsif pulse_i = '1' then
+          level <= '1';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  level_o <= level;
+
+end rtl;
+