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Beam Positoning Monitor - Gateware
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Beam Positoning Monitor - Gateware
Commits
debef298
Commit
debef298
authored
Feb 27, 2013
by
Adrian Byszuk
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Add AREA constraints to prevent timing errors
parent
9f15ca7f
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2 changed files
with
10 additions
and
12 deletions
+10
-12
bpm_pcie_a7.xise
hdl/syn/pcie/bpm_pcie_a7.xise
+3
-3
xc7a200tffg1156.ucf
hdl/syn/pcie/xc7a200tffg1156.ucf
+7
-9
No files found.
hdl/syn/pcie/bpm_pcie_a7.xise
View file @
debef298
...
...
@@ -114,7 +114,7 @@
<property
xil_pn:name=
"Generate Constraints Interaction Report Post Trace"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Datasheet Section"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Datasheet Section Post Trace"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Detailed MAP Report"
xil_pn:value=
"
false"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Generate Detailed MAP Report"
xil_pn:value=
"
true"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Generate Multiple Hierarchical Netlist Files"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Post-Place & Route Power Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Post-Place & Route Simulation Model"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
...
@@ -122,7 +122,7 @@
<property
xil_pn:name=
"Generate SAIF File for Power Optimization/Estimation Par"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Testbench File"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Timegroups Section"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Timegroups Section Post Trace"
xil_pn:value=
"
false"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Generate Timegroups Section Post Trace"
xil_pn:value=
"
true"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Generics, Parameters"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Global Optimization Goal"
xil_pn:value=
"AllClockNets"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Global Optimization map virtex5"
xil_pn:value=
"Off"
xil_pn:valueState=
"default"
/>
...
...
@@ -167,7 +167,7 @@
<property
xil_pn:name=
"Move First Flip-Flop Stage"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Move Last Flip-Flop Stage"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"MultiBoot: Insert IPROG CMD in the Bitfile virtex7"
xil_pn:value=
"Enable"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Netlist Hierarchy"
xil_pn:value=
"
As Optimized"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Netlist Hierarchy"
xil_pn:value=
"
Rebuilt"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Netlist Translation Type"
xil_pn:value=
"Timestamp"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Number of Clock Buffers"
xil_pn:value=
"32"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Number of Paths in Error/Verbose Report"
xil_pn:value=
"3"
xil_pn:valueState=
"default"
/>
...
...
hdl/syn/pcie/xc7a200tffg1156.ucf
View file @
debef298
...
...
@@ -129,12 +129,6 @@ NET "ddr_sys_clk_n" LOC = "AL7" | IOSTANDARD = D
#########################################################################################################################
# End User Constraints
#########################################################################################################################
#
#
#
#########################################################################################################################
# PCIE Core Constraints
#########################################################################################################################
###############################################################################
# Pinout and Related I/O Constraints
...
...
@@ -297,8 +291,12 @@ TIMESPEC "TS_MULTICYCLEPATH_DEVICE_TEMP_SYNC" = TO "TNM_MULTICYCLEPATH_DEVICE_TE
###############################################################################
# Physical Constraints
###############################################################################
#########################################################################################################################
# End PCIe Core Constraints
#########################################################################################################################
# Constrain the PCIe core elements placement, so that it won't fail
# timing analysis.
INST "pcie_core_i" AREA_GROUP = "GRP_PCIE_CORE";
AREA_GROUP "GRP_PCIE_CORE" RANGE = CLOCKREGION_X0Y4;
#Place the DMA design not far from PCIe core, otherwise it also breaks timing
INST "theTlpControl" AREA_GROUP = "GRP_tlpControl";
AREA_GROUP "GRP_tlpControl" RANGE = CLOCKREGION_X0Y2:CLOCKREGION_X0Y4;
# PlanAhead Generated physical constraints
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