Added chipscope component "vio" with 16 synchronous outputs

e6ba6ab0 · Vitor Finotti · 511454f6 · e6ba6ab0 · e6ba6ab0 · e6ba6ab0
Commit e6ba6ab0 authored Jan 14, 2016 by Vitor Finotti
3 changed files
--- a/hdl/platform/artix7/chipscope/Manifest.py
+++ b/hdl/platform/artix7/chipscope/Manifest.py
@@ -11,5 +11,7 @@ files = [
 	"ila/chipscope_ila_rcv.vhd",
        "vio/chipscope_vio_32.vhd",
        "vio/chipscope_vio_32.ngc",
+	"vio/chipscope_vio_16.vhd",
+        "vio/chipscope_vio_16.ngc",
        "vio/chipscope_vio_8.vhd",
        "vio/chipscope_vio_8.ngc"]
--- a/hdl/platform/artix7/chipscope/vio/chipscope_vio_16.ngc
+++ b/hdl/platform/artix7/chipscope/vio/chipscope_vio_16.ngc
--- a/hdl/platform/artix7/chipscope/vio/chipscope_vio_16.vhd
+++ b/hdl/platform/artix7/chipscope/vio/chipscope_vio_16.vhd
+-------------------------------------------------------------------------------
+-- Copyright (c) 2016 Xilinx, Inc.
+-- All Rights Reserved
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor     : Xilinx
+-- \   \   \/     Version    : 14.7
+--  \   \         Application: XILINX CORE Generator
+--  /   /         Filename   : chipscope_vio_16.vhd
+-- /___/   /\     Timestamp  : Tue Jan 12 15:32:26 BRST 2016
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Design Name: VHDL Synthesis Wrapper
+-------------------------------------------------------------------------------
+-- This wrapper is used to integrate with Project Navigator and PlanAhead
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY chipscope_vio_16 IS
+  port (
+    CONTROL: inout std_logic_vector(35 downto 0);
+    CLK: in std_logic;
+    SYNC_OUT: out std_logic_vector(15 downto 0));
+END chipscope_vio_16;
+
+ARCHITECTURE chipscope_vio_16_a OF chipscope_vio_16 IS
+BEGIN
+
+END chipscope_vio_16_a;