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Commit e7e716e0 authored by Lucas Russo's avatar Lucas Russo
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wb_fmc150/*: minor updates and sanitization

parent b549920a
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hdl/modules/custom_wishbone/wb_fmc150/Manifest.py
View file @ e7e716e0
modules = { "local" : [ files = ["wb_fmc150.vhd", "xwb_fmc150.vhd", "xfmc150_regs_pkg.vhd", "wb_fmc150_port.vhd"];
"adc",
"fmc150", # Select between synthesis or simulation components
"netlist" ] }; if (action == "synthesis" ):
if(target == "xilinx" and syn_device[0:4].upper()=="XC6V"):
modules = {"local" : [ "adc", "fmc150", "netlist"]}
else:
print "WARNING: Device not supported for synthesis using the FMC150 core!"
elif (action == "simulation"):
if (target == "xilinx"):
modules = {"local" : [ "adc", "fmc150", "sim"]}
else:
print "WARNING: Device not supported for simulation using the FMC150 core!"
# It will not reach nthis point as hdlmake takes cares of unsupported options
#else:
# "WARNING: Device not supported using the FMC150 core!"
files = ["wb_fmc150.vhd", "xwb_fmc150.vhd", "xfmc150_regs_pkg.vhd", "wb_fmc150_port.vhd" ];
hdl/modules/custom_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd
View file @ e7e716e0
...@@ -27,6 +27,10 @@ library ieee; ...@@ -27,6 +27,10 @@ library ieee;
use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all; use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;
-- Memoryies NGC
library UNISIM;
use UNISIM.vcomponents.all;
entity ads62p49_ctrl is entity ads62p49_ctrl is
generic ( generic (
...@@ -146,6 +150,7 @@ signal inst_reg : std_logic_vector(7 downto 0); ...@@ -146,6 +150,7 @@ signal inst_reg : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0);
signal sh_counter : integer; signal sh_counter : integer;
signal sh_counter_gen : integer;
signal shifting : std_logic; signal shifting : std_logic;
signal read_n_write : std_logic; signal read_n_write : std_logic;
signal ncs_int : std_logic; signal ncs_int : std_logic;
...@@ -317,6 +322,13 @@ port map ...@@ -317,6 +322,13 @@ port map
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- Serial interface state-machine -- Serial interface state-machine
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
--gen_sh_counter : if (g_sim = 0) generate
sh_counter_gen <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
--end generate;
--gen_sh_counter_sim : if (g_sim = 1) generate
-- sh_counter_gen <= 1;
--end generate;
process (rst, serial_clk) process (rst, serial_clk)
begin begin
...@@ -340,7 +352,8 @@ begin ...@@ -340,7 +352,8 @@ begin
case sh_state is case sh_state is
when idle => when idle =>
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus data bytes; sh_counter <= sh_counter_gen;
-- Accept every instruction -- Accept every instruction
if (inst_reg_val = '1' or init_reg = '1') then if (inst_reg_val = '1' or init_reg = '1') then
shifting <= '1'; shifting <= '1';
......
hdl/modules/custom_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd
View file @ e7e716e0
...@@ -27,6 +27,10 @@ library ieee; ...@@ -27,6 +27,10 @@ library ieee;
use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all; use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;
-- Memoryies NGC
library UNISIM;
use UNISIM.vcomponents.all;
entity amc7823_ctrl is entity amc7823_ctrl is
generic ( generic (
...@@ -148,6 +152,7 @@ signal inst_reg : std_logic_vector(4 downto 0); ...@@ -148,6 +152,7 @@ signal inst_reg : std_logic_vector(4 downto 0);
signal data_reg : std_logic_vector(15 downto 0); signal data_reg : std_logic_vector(15 downto 0);
signal sh_counter : integer; signal sh_counter : integer;
signal sh_counter_gen : integer;
signal shifting : std_logic; signal shifting : std_logic;
signal read_n_write : std_logic; signal read_n_write : std_logic;
signal ncs_int : std_logic; signal ncs_int : std_logic;
...@@ -322,6 +327,13 @@ port map ...@@ -322,6 +327,13 @@ port map
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- DAC serial interface state-machine -- DAC serial interface state-machine
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
--gen_sh_counter : if (g_sim = 0) generate
sh_counter_gen <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
--end generate;
--gen_sh_counter_sim : if (g_sim = 1) generate
-- sh_counter_gen <= 1;
--end generate;
process (rst, serial_clk) process (rst, serial_clk)
begin begin
...@@ -345,7 +357,8 @@ begin ...@@ -345,7 +357,8 @@ begin
case sh_state is case sh_state is
when idle => when idle =>
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus one data byte; sh_counter <= sh_counter_gen;
-- Accept every instruction -- Accept every instruction
if (inst_reg_val = '1' or init_reg = '1') then if (inst_reg_val = '1' or init_reg = '1') then
shifting <= '1'; shifting <= '1';
......
hdl/modules/custom_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd
View file @ e7e716e0
...@@ -22,11 +22,17 @@ ...@@ -22,11 +22,17 @@
-- through SPI communication bus. -- through SPI communication bus.
-- --
------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------
-- Modified by Lucas Russo <lucas.russo@lnls.br>
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all; use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;
-- Memoryies NGC
library UNISIM;
use UNISIM.vcomponents.all;
entity cdce72010_ctrl is entity cdce72010_ctrl is
generic ( generic (
...@@ -161,6 +167,7 @@ signal inst_reg : std_logic_vector(3 downto 0); ...@@ -161,6 +167,7 @@ signal inst_reg : std_logic_vector(3 downto 0);
signal data_reg : std_logic_vector(27 downto 0); signal data_reg : std_logic_vector(27 downto 0);
signal sh_counter : integer; signal sh_counter : integer;
signal sh_counter_gen : integer;
signal shifting : std_logic; signal shifting : std_logic;
signal read_n_write : std_logic; signal read_n_write : std_logic;
signal ncs_int : std_logic; signal ncs_int : std_logic;
...@@ -341,6 +348,14 @@ port map ...@@ -341,6 +348,14 @@ port map
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- DAC serial interface state-machine -- DAC serial interface state-machine
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- Speedup simulation execution
--gen_sh_counter : if (g_sim = 0) generate
sh_counter_gen <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
--end generate;
--gen_sh_counter_sim : if (g_sim = 1) generate
-- sh_counter_gen <= 2;
--end generate;
process (rst, serial_clk) process (rst, serial_clk)
begin begin
...@@ -364,7 +379,8 @@ begin ...@@ -364,7 +379,8 @@ begin
case sh_state is case sh_state is
when idle => when idle =>
sh_counter <= shift_reg'length - 1; sh_counter <= sh_counter_gen;
-- Accept every instruction -- Accept every instruction
if (inst_reg_val = '1' or init_reg = '1') then if (inst_reg_val = '1' or init_reg = '1') then
shifting <= '1'; shifting <= '1';
......
hdl/modules/custom_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd
View file @ e7e716e0
...@@ -27,6 +27,10 @@ library ieee; ...@@ -27,6 +27,10 @@ library ieee;
use ieee.std_logic_arith.all; use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all; use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;
-- Memoryies NGC
library UNISIM;
use UNISIM.vcomponents.all;
entity dac3283_ctrl is entity dac3283_ctrl is
generic ( generic (
...@@ -143,6 +147,7 @@ signal inst_reg : std_logic_vector(4 downto 0); ...@@ -143,6 +147,7 @@ signal inst_reg : std_logic_vector(4 downto 0);
signal data_reg : std_logic_vector(7 downto 0); signal data_reg : std_logic_vector(7 downto 0);
signal sh_counter : integer; signal sh_counter : integer;
signal sh_counter_gen : integer;
signal shifting : std_logic; signal shifting : std_logic;
signal read_n_write : std_logic; signal read_n_write : std_logic;
signal ncs_int : std_logic; signal ncs_int : std_logic;
...@@ -306,6 +311,14 @@ port map ...@@ -306,6 +311,14 @@ port map
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- Serial interface state-machine -- Serial interface state-machine
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- Speedup simulation execution
--gen_sh_counter : if (g_sim = 0) generate
sh_counter_gen <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
--end generate;
--gen_sh_counter_sim : if (g_sim = 1) generate
-- sh_counter_gen <= 1;
--end generate;
process (rst, serial_clk) process (rst, serial_clk)
begin begin
...@@ -329,7 +342,8 @@ begin ...@@ -329,7 +342,8 @@ begin
case sh_state is case sh_state is
when idle => when idle =>
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus data bytes; sh_counter <= sh_counter_gen;
-- Accept every instruction -- Accept every instruction
if (inst_reg_val = '1' or init_reg = '1') then if (inst_reg_val = '1' or init_reg = '1') then
shifting <= '1'; shifting <= '1';
......
hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd
View file @ e7e716e0
...@@ -363,7 +363,7 @@ package fmc150_pkg is ...@@ -363,7 +363,7 @@ package fmc150_pkg is
( (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000"; START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"; STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF";
g_sim : integer := 0 g_sim : integer := 0
); );
port port
( (
......
hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150.vhd
View file @ e7e716e0
...@@ -188,7 +188,7 @@ architecture rtl of wb_fmc150 is ...@@ -188,7 +188,7 @@ architecture rtl of wb_fmc150 is
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
wb_stall_o : out std_logic; wb_stall_o : out std_logic;
clk_100Mhz_i : in std_logic; clk_100Mhz_i : in std_logic;
clk_wb_i : in std_logic; --clk_wb_i : in std_logic;
regs_i : in t_fmc150_in_registers; regs_i : in t_fmc150_in_registers;
regs_o : out t_fmc150_out_registers regs_o : out t_fmc150_out_registers
); );
...@@ -401,7 +401,7 @@ begin ...@@ -401,7 +401,7 @@ begin
wb_ack_o => wb_out.ack, wb_ack_o => wb_out.ack,
wb_stall_o => wb_out.stall, wb_stall_o => wb_out.stall,
clk_100Mhz_i => clk_100Mhz_i, clk_100Mhz_i => clk_100Mhz_i,
clk_wb_i => clk_sys_i, --clk_wb_i => clk_sys_i,
regs_i => regs_out, regs_i => regs_out,
regs_o => regs_in regs_o => regs_in
); );
...@@ -409,7 +409,7 @@ begin ...@@ -409,7 +409,7 @@ begin
-- Reset synchronization with ADC clock domain -- Reset synchronization with ADC clock domain
cmp_reset_adc_synch : reset_synch cmp_reset_adc_synch : reset_synch
port map( port map(
clk_i => s_clk_adc, clk_i => s_clk_adc,
arst_n_i => rst_n_i, arst_n_i => rst_n_i,
rst_n_o => rst_n_adc rst_n_o => rst_n_adc
); );
...@@ -440,25 +440,7 @@ begin ...@@ -440,25 +440,7 @@ begin
s_addr <= (others => '0'); s_addr <= (others => '0');
-- Simulation / Syntesis Only consructs. Is there a better way to do it? -- Simulation / Syntesis Only consructs. Is there a better way to do it?
--gen_stream_data : if (g_sim = 0) generate s_data <= s_adc_dout(c_wbs_data_width-1 downto 0);
s_data <= s_adc_dout(c_wbs_data_width-1 downto 0);
--end generate;
--gen_stream_data_sim : if (g_sim = 1) generate
-- p_gen_data_sim : process--(s_clk_adc, rst_n_i)
-- variable seed1, seed2: positive; -- Seed values for random generator
-- begin
-- seed1 := 432566;
-- seed2 := 211;
-- s_data <= (others => '0');
-- -- Wait until reset completion (synch with adc clock domain)
-- wait until rst_n_adc = '1';
-- l_generate_data: loop
-- gen_data(c_wbs_data_width, seed1, seed2, s_data);
-- wait until rising_edge(s_clk_adc);
-- end loop;
-- end process;
--end generate;
gen_stream_valid : if (g_sim = 0) generate gen_stream_valid : if (g_sim = 0) generate
s_dvalid <= cdce_pll_status_i and s_mmcm_adc_locked; s_dvalid <= cdce_pll_status_i and s_mmcm_adc_locked;
...@@ -467,42 +449,15 @@ begin ...@@ -467,42 +449,15 @@ begin
gen_stream_valid_sim : if (g_sim = 1) generate gen_stream_valid_sim : if (g_sim = 1) generate
s_dvalid <= sim_adc_data_valid; s_dvalid <= sim_adc_data_valid;
end generate; end generate;
--gen_stream_valid_sim : if (g_sim = 1) generate -- generate SOF and EOF signals
-- p_gen_valid_sim : process--(s_clk_adc, rst_n_i)
-- variable seed1, seed2: positive; -- Seed values for random generator
-- begin
-- seed1 := 67632;
-- seed2 := 3234;
-- s_dvalid <= '0';
-- -- Wait until reset completion (synch with adc clock domain)
-- wait until rst_n_adc = '1';
-- l_generate_valid: loop
-- gen_valid(0.5, seed1, seed2, s_dvalid);
-- wait until rising_edge(s_clk_adc);
-- end loop;
-- end process;
--end generate;
p_gen_sof_eof : process(s_clk_adc, rst_n_i) p_gen_sof_eof : process(s_clk_adc, rst_n_i)
begin begin
if rst_n_adc = '0' then if rst_n_adc = '0' then
--s_sof <= '0'; --s_sof <= '0';
--s_eof <= '0'; --s_eof <= '0';
s_wbs_packet_counter <= (others => '0'); s_wbs_packet_counter <= (others => '0');
elsif rising_edge(s_clk_adc) then elsif rising_edge(s_clk_adc) then
-- Defaults assignments
--s_sof <= '0';
--s_eof <= '0';
-- Finish current transaction
--if(s_wbs_packet_counter = g_packet_size-1) then
-- s_eof <= '1';
-- --s_wbs_packet_counter <= (others => '0');
--elsif (s_wbs_packet_counter = to_unsigned(0, c_counter_size)) then
-- s_sof <= '1';
--end if;
-- Increment counter if data is valid -- Increment counter if data is valid
if s_dvalid = '1' then if s_dvalid = '1' then
s_wbs_packet_counter <= s_wbs_packet_counter + 1; s_wbs_packet_counter <= s_wbs_packet_counter + 1;
......
hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150_port.vhd
View file @ e7e716e0
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : wb_fmc150_port.vhd -- File : wb_fmc150_port.vhd
-- Author : auto-generated by wbgen2 from xfmc150.wb -- Author : auto-generated by wbgen2 from xfmc150.wb
-- Created : Mon Oct 8 11:24:05 2012 -- Created : Tue Oct 9 14:47:14 2012
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb
...@@ -31,7 +31,6 @@ entity wb_fmc150_port is ...@@ -31,7 +31,6 @@ entity wb_fmc150_port is
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
wb_stall_o : out std_logic; wb_stall_o : out std_logic;
clk_100Mhz_i : in std_logic; clk_100Mhz_i : in std_logic;
clk_wb_i : in std_logic;
regs_i : in t_fmc150_in_registers; regs_i : in t_fmc150_in_registers;
regs_o : out t_fmc150_out_registers regs_o : out t_fmc150_out_registers
); );
...@@ -92,17 +91,6 @@ signal fmc150_adc_dly_chb_swb_delay : std_logic ; ...@@ -92,17 +91,6 @@ signal fmc150_adc_dly_chb_swb_delay : std_logic ;
signal fmc150_adc_dly_chb_swb_s0 : std_logic ; signal fmc150_adc_dly_chb_swb_s0 : std_logic ;
signal fmc150_adc_dly_chb_swb_s1 : std_logic ; signal fmc150_adc_dly_chb_swb_s1 : std_logic ;
signal fmc150_adc_dly_chb_swb_s2 : std_logic ; signal fmc150_adc_dly_chb_swb_s2 : std_logic ;
signal fmc150_data_out_int : std_logic_vector(31 downto 0);
signal fmc150_data_out_lwb : std_logic ;
signal fmc150_data_out_lwb_delay : std_logic ;
signal fmc150_data_out_lwb_in_progress : std_logic ;
signal fmc150_data_out_lwb_s0 : std_logic ;
signal fmc150_data_out_lwb_s1 : std_logic ;
signal fmc150_data_out_lwb_s2 : std_logic ;
signal fmc150_flgs_out_spi_busy_sync0 : std_logic ;
signal fmc150_flgs_out_spi_busy_sync1 : std_logic ;
signal fmc150_flgs_out_adc_clk_locked_sync0 : std_logic ;
signal fmc150_flgs_out_adc_clk_locked_sync1 : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0); signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0); signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0); signal wrdata_reg : std_logic_vector(31 downto 0);
...@@ -153,9 +141,6 @@ begin ...@@ -153,9 +141,6 @@ begin
fmc150_adc_dly_chb_int <= "00000"; fmc150_adc_dly_chb_int <= "00000";
fmc150_adc_dly_chb_swb <= '0'; fmc150_adc_dly_chb_swb <= '0';
fmc150_adc_dly_chb_swb_delay <= '0'; fmc150_adc_dly_chb_swb_delay <= '0';
fmc150_data_out_lwb <= '0';
fmc150_data_out_lwb_delay <= '0';
fmc150_data_out_lwb_in_progress <= '0';
elsif rising_edge(clk_sys_i) then elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register -- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1); ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
...@@ -176,12 +161,6 @@ begin ...@@ -176,12 +161,6 @@ begin
fmc150_adc_dly_cha_swb_delay <= '0'; fmc150_adc_dly_cha_swb_delay <= '0';
fmc150_adc_dly_chb_swb <= fmc150_adc_dly_chb_swb_delay; fmc150_adc_dly_chb_swb <= fmc150_adc_dly_chb_swb_delay;
fmc150_adc_dly_chb_swb_delay <= '0'; fmc150_adc_dly_chb_swb_delay <= '0';
fmc150_data_out_lwb <= fmc150_data_out_lwb_delay;
fmc150_data_out_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc150_data_out_lwb_in_progress = '1')) then
rddata_reg(31 downto 0) <= fmc150_data_out_int;
fmc150_data_out_lwb_in_progress <= '0';
end if;
end if; end if;
else else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
...@@ -376,18 +355,14 @@ begin ...@@ -376,18 +355,14 @@ begin
when "110" => when "110" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
if (wb_we_i = '0') then rddata_reg(31 downto 0) <= regs_i.data_out_i;
fmc150_data_out_lwb <= '1'; ack_sreg(0) <= '1';
fmc150_data_out_lwb_delay <= '1';
fmc150_data_out_lwb_in_progress <= '1';
end if;
ack_sreg(5) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "111" => when "111" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(0) <= fmc150_flgs_out_spi_busy_sync1; rddata_reg(0) <= regs_i.flgs_out_spi_busy_i;
rddata_reg(1) <= fmc150_flgs_out_adc_clk_locked_sync1; rddata_reg(1) <= regs_i.flgs_out_adc_clk_locked_i;
rddata_reg(2) <= 'X'; rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X'; rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X'; rddata_reg(4) <= 'X';
...@@ -647,53 +622,8 @@ begin ...@@ -647,53 +622,8 @@ begin
-- Data out from FMC150 -- Data out from FMC150
-- asynchronous std_logic_vector register : Data out from FMC150 (type RO/WO, clk_wb_i <-> clk_sys_i)
process (clk_wb_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc150_data_out_lwb_s0 <= '0';
fmc150_data_out_lwb_s1 <= '0';
fmc150_data_out_lwb_s2 <= '0';
fmc150_data_out_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_wb_i) then
fmc150_data_out_lwb_s0 <= fmc150_data_out_lwb;
fmc150_data_out_lwb_s1 <= fmc150_data_out_lwb_s0;
fmc150_data_out_lwb_s2 <= fmc150_data_out_lwb_s1;
if ((fmc150_data_out_lwb_s1 = '1') and (fmc150_data_out_lwb_s2 = '0')) then
fmc150_data_out_int <= regs_i.data_out_i;
end if;
end if;
end process;
-- SPI Busy -- SPI Busy
-- SPI Busy
-- synchronizer chain for field : SPI Busy (type RO/WO, clk_wb_i -> clk_sys_i)
process (clk_wb_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc150_flgs_out_spi_busy_sync0 <= '0';
fmc150_flgs_out_spi_busy_sync1 <= '0';
elsif rising_edge(clk_wb_i) then
fmc150_flgs_out_spi_busy_sync0 <= regs_i.flgs_out_spi_busy_i;
fmc150_flgs_out_spi_busy_sync1 <= fmc150_flgs_out_spi_busy_sync0;
end if;
end process;
-- FPGA ADC clock locked -- FPGA ADC clock locked
-- FPGA ADC clock locked
-- synchronizer chain for field : FPGA ADC clock locked (type RO/WO, clk_wb_i -> clk_sys_i)
process (clk_wb_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc150_flgs_out_adc_clk_locked_sync0 <= '0';
fmc150_flgs_out_adc_clk_locked_sync1 <= '0';
elsif rising_edge(clk_wb_i) then
fmc150_flgs_out_adc_clk_locked_sync0 <= regs_i.flgs_out_adc_clk_locked_i;
fmc150_flgs_out_adc_clk_locked_sync1 <= fmc150_flgs_out_adc_clk_locked_sync0;
end if;
end process;
rwaddr_reg <= wb_adr_i; rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i); wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter. -- ACK signal generation. Just pass the LSB of ACK counter.
......
hdl/modules/custom_wishbone/wb_fmc150/xfmc150.wb
View file @ e7e716e0
...@@ -181,6 +181,7 @@ peripheral { ...@@ -181,6 +181,7 @@ peripheral {
}; };
}; };
-- I don't think the below is true anymore. Check!
-- The following registers are within the clk_100Mhz_i domain. -- The following registers are within the clk_100Mhz_i domain.
-- Therefore, in order to read it from the bus, we need -- Therefore, in order to read it from the bus, we need
-- to synchronize them to clk_wb_i (wishbone control clock) domain. -- to synchronize them to clk_wb_i (wishbone control clock) domain.
...@@ -197,10 +198,9 @@ peripheral { ...@@ -197,10 +198,9 @@ peripheral {
name = "Data out from FMC150"; name = "Data out from FMC150";
description = "Data from internal chip register"; description = "Data from internal chip register";
--prefix = "data"; --prefix = "data";
type = SLV; type = SLV;
size = 32; size = 32;
--clock = "clk_100Mhz"; --clock = "clk_wb_i";
clock = "clk_wb_i";
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
...@@ -216,9 +216,8 @@ peripheral { ...@@ -216,9 +216,8 @@ peripheral {
description = "read 1: spi busy.\ description = "read 1: spi busy.\
read 0: spi idle"; read 0: spi idle";
prefix = "spi_busy"; prefix = "spi_busy";
type = BIT; type = BIT;
--clock = "clk_100Mhz"; --clock = "clk_wb_i";
clock = "clk_wb_i";
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
...@@ -240,9 +239,8 @@ peripheral { ...@@ -240,9 +239,8 @@ peripheral {
description = "read 1: FPGA ADC PLL locked.\ description = "read 1: FPGA ADC PLL locked.\
read 0: FPGA ADC PLL not locked"; read 0: FPGA ADC PLL not locked";
prefix = "adc_clk_locked"; prefix = "adc_clk_locked";
type = BIT; type = BIT;
--clock = "clk_100Mhz"; --clock = "clk_wb_i";
clock = "clk_wb_i";
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
...@@ -261,6 +259,3 @@ peripheral { ...@@ -261,6 +259,3 @@ peripheral {
}; };
}; };
hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd
View file @ e7e716e0
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : xfmc150_regs_pkg.vhd -- File : xfmc150_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from xfmc150.wb -- Author : auto-generated by wbgen2 from xfmc150.wb
-- Created : Mon Oct 8 11:24:05 2012 -- Created : Tue Oct 9 14:47:14 2012
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb
......
hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_regs.h
View file @ e7e716e0
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : xfmc150_regs_regs.h * File : xfmc150_regs_regs.h
* Author : auto-generated by wbgen2 from xfmc150.wb * Author : auto-generated by wbgen2 from xfmc150.wb
* Created : Mon Oct 8 11:24:05 2012 * Created : Tue Oct 9 14:47:14 2012
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb
......
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