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Commit e975bc03 authored by Lucas Russo's avatar Lucas Russo
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fmc_active_clk/*: add dummy register so we can connect adr bus to module

parent 7ae86fea
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hdl/modules/fmc_adc_common/fmc_active_clk/wbgen/doc/fmc_active_clk_regs_wb.html
View file @ e975bc03
......@@ -35,6 +35,7 @@
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Clock distribution control register</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Dummy</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -71,6 +72,23 @@ wb_fmc_active_clk_csr_clk_distrib
CLK_DISTRIB
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x1
</td>
<td >
REG
</td>
<td >
<A href="#DUMMY">Dummy</a>
</td>
<td class="td_code">
wb_fmc_active_clk_csr_dummy
</td>
<td class="td_code">
DUMMY
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
......@@ -111,10 +129,10 @@ wb_fmc_active_clk_csr_clk_distrib_si571_oe_o
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
&rarr;
</td>
<td class="td_pblock_left">
wb_dat_i[31:0]
wb_adr_i
</td>
<td class="td_sym_center">
......@@ -128,10 +146,10 @@ wb_fmc_active_clk_csr_clk_distrib_pll_function_o
</tr>
<tr>
<td class="td_arrow_left">
&lArr;
&rArr;
</td>
<td class="td_pblock_left">
wb_dat_o[31:0]
wb_dat_i[31:0]
</td>
<td class="td_sym_center">
......@@ -145,10 +163,10 @@ wb_fmc_active_clk_csr_clk_distrib_pll_status_i
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
&lArr;
</td>
<td class="td_pblock_left">
wb_cyc_i
wb_dat_o[31:0]
</td>
<td class="td_sym_center">
......@@ -162,10 +180,10 @@ wb_fmc_active_clk_csr_clk_distrib_clk_sel_o
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
&rarr;
</td>
<td class="td_pblock_left">
wb_sel_i[3:0]
wb_cyc_i
</td>
<td class="td_sym_center">
......@@ -175,6 +193,23 @@ wb_fmc_active_clk_csr_clk_distrib_reserved_i[27:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_sel_i[3:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
......@@ -188,7 +223,7 @@ wb_stb_i
</td>
<td class="td_pblock_right">
<b>Dummy:</b>
</td>
<td class="td_arrow_right">
......@@ -205,10 +240,10 @@ wb_we_i
</td>
<td class="td_pblock_right">
wb_fmc_active_clk_csr_dummy_reserved_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
......@@ -522,6 +557,264 @@ RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's.
</ul>
<a name="DUMMY"></a>
<h3><a name="sect_3_2">3.2. Dummy</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
wb_fmc_active_clk_csr_dummy
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
DUMMY
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's.
</ul>
......
hdl/modules/fmc_adc_common/fmc_active_clk/wbgen/wb_fmc_active_clk_regs.h
View file @ e975bc03
......@@ -3,7 +3,7 @@
* File : wb_fmc_active_clk_regs.h
* Author : auto-generated by wbgen2 from wb_fmc_active_clk_regs.wb
* Created : Mon Apr 18 09:07:08 2016
* Created : Mon Apr 18 10:20:28 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_active_clk_regs.wb
......@@ -50,6 +50,16 @@
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_SHIFT 4
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Dummy */
/* definitions for field: Reserved in reg: Dummy */
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_MASK WBGEN2_GEN_MASK(0, 32)
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_SHIFT 0
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* [0x0]: REG Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_REG_CLK_DISTRIB 0x00000000
/* [0x4]: REG Dummy */
#define WB_FMC_ACTIVE_CLK_CSR_REG_DUMMY 0x00000004
#endif
hdl/modules/fmc_adc_common/fmc_active_clk/wbgen/wb_fmc_active_clk_regs.vhd
View file @ e975bc03
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wb_fmc_active_clk_regs.vhd
-- Author : auto-generated by wbgen2 from wb_fmc_active_clk_regs.wb
-- Created : Mon Apr 18 09:07:08 2016
-- Created : Mon Apr 18 10:20:28 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_active_clk_regs.wb
......@@ -21,6 +21,7 @@ entity wb_fmc_active_clk_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(0 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
......@@ -80,18 +81,31 @@ begin
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
if (wb_we_i = '1') then
wb_fmc_active_clk_csr_clk_distrib_si571_oe_int <= wrdata_reg(0);
wb_fmc_active_clk_csr_clk_distrib_pll_function_int <= wrdata_reg(1);
wb_fmc_active_clk_csr_clk_distrib_clk_sel_int <= wrdata_reg(3);
end if;
rddata_reg(0) <= wb_fmc_active_clk_csr_clk_distrib_si571_oe_int;
rddata_reg(1) <= wb_fmc_active_clk_csr_clk_distrib_pll_function_int;
rddata_reg(2) <= regs_i.clk_distrib_pll_status_i;
rddata_reg(3) <= wb_fmc_active_clk_csr_clk_distrib_clk_sel_int;
rddata_reg(31 downto 4) <= regs_i.clk_distrib_reserved_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
case rwaddr_reg(0) is
when '0' =>
if (wb_we_i = '1') then
wb_fmc_active_clk_csr_clk_distrib_si571_oe_int <= wrdata_reg(0);
wb_fmc_active_clk_csr_clk_distrib_pll_function_int <= wrdata_reg(1);
wb_fmc_active_clk_csr_clk_distrib_clk_sel_int <= wrdata_reg(3);
end if;
rddata_reg(0) <= wb_fmc_active_clk_csr_clk_distrib_si571_oe_int;
rddata_reg(1) <= wb_fmc_active_clk_csr_clk_distrib_pll_function_int;
rddata_reg(2) <= regs_i.clk_distrib_pll_status_i;
rddata_reg(3) <= wb_fmc_active_clk_csr_clk_distrib_clk_sel_int;
rddata_reg(31 downto 4) <= regs_i.clk_distrib_reserved_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when '1' =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.dummy_reserved_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
......@@ -108,7 +122,8 @@ begin
-- Reference Clock Selection
regs_o.clk_distrib_clk_sel_o <= wb_fmc_active_clk_csr_clk_distrib_clk_sel_int;
-- Reserved
rwaddr_reg <= (others => '0');
-- Reserved
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
......
hdl/modules/fmc_adc_common/fmc_active_clk/wbgen/wb_fmc_active_clk_regs.wb
View file @ e975bc03
......@@ -4,7 +4,7 @@ peripheral {
hdl_entity = "wb_fmc_active_clk_csr";
prefix = "wb_fmc_active_clk_csr";
reg {
reg {
name = "Clock distribution control register";
prefix = "clk_distrib";
......@@ -59,4 +59,19 @@ peripheral {
};
};
reg {
name = "Dummy";
prefix = "dummy";
field {
name = "Reserved";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
hdl/modules/fmc_adc_common/fmc_active_clk/wbgen/wb_fmc_active_clk_regs_pkg.vhd
View file @ e975bc03
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wb_fmc_active_clk_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from wb_fmc_active_clk_regs.wb
-- Created : Mon Apr 18 09:07:08 2016
-- Created : Mon Apr 18 10:20:28 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_active_clk_regs.wb
......@@ -22,11 +22,13 @@ package wb_fmc_active_clk_csr_wbgen2_pkg is
type t_wb_fmc_active_clk_csr_in_registers is record
clk_distrib_pll_status_i : std_logic;
clk_distrib_reserved_i : std_logic_vector(27 downto 0);
dummy_reserved_i : std_logic_vector(31 downto 0);
end record;
constant c_wb_fmc_active_clk_csr_in_registers_init_value: t_wb_fmc_active_clk_csr_in_registers := (
clk_distrib_pll_status_i => '0',
clk_distrib_reserved_i => (others => '0')
clk_distrib_reserved_i => (others => '0'),
dummy_reserved_i => (others => '0')
);
-- Output registers (WB slave -> user design)
......@@ -73,6 +75,7 @@ variable tmp: t_wb_fmc_active_clk_csr_in_registers;
begin
tmp.clk_distrib_pll_status_i := f_x_to_zero(left.clk_distrib_pll_status_i) or f_x_to_zero(right.clk_distrib_pll_status_i);
tmp.clk_distrib_reserved_i := f_x_to_zero(left.clk_distrib_reserved_i) or f_x_to_zero(right.clk_distrib_reserved_i);
tmp.dummy_reserved_i := f_x_to_zero(left.dummy_reserved_i) or f_x_to_zero(right.dummy_reserved_i);
return tmp;
end function;
end package body;
hdl/sim/regs/wb_fmc_active_clk_regs.vh
View file @ e975bc03
`define ADDR_WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB 2'h0
`define ADDR_WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB 3'h0
`define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_SI571_OE_OFFSET 0
`define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_SI571_OE 32'h00000001
`define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_PLL_FUNCTION_OFFSET 1
......@@ -9,3 +9,6 @@
`define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_CLK_SEL 32'h00000008
`define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_OFFSET 4
`define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED 32'hfffffff0
`define ADDR_WB_FMC_ACTIVE_CLK_CSR_DUMMY 3'h4
`define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_OFFSET 0
`define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED 32'hffffffff
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