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Beam Positoning Monitor - Gateware
Commits
ec013494
Commit
ec013494
authored
Dec 12, 2012
by
Lucas Russo
Browse files
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fabric/: add fabric interface (from wr-cores repo)
parent
bee2aa25
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4 changed files
with
558 additions
and
0 deletions
+558
-0
Manifest.py
hdl/modules/fabric/Manifest.py
+1
-0
wr_fabric_pkg.vhd
hdl/modules/fabric/wr_fabric_pkg.vhd
+96
-0
xwb_fabric_sink.vhd
hdl/modules/fabric/xwb_fabric_sink.vhd
+265
-0
xwb_fabric_source.vhd
hdl/modules/fabric/xwb_fabric_source.vhd
+196
-0
No files found.
hdl/modules/fabric/Manifest.py
0 → 100644
View file @
ec013494
files
=
[
"wr_fabric_pkg.vhd"
,
"xwb_fabric_sink.vhd"
,
"xwb_fabric_source.vhd"
]
\ No newline at end of file
hdl/modules/fabric/wr_fabric_pkg.vhd
0 → 100644
View file @
ec013494
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
package
wr_fabric_pkg
is
constant
c_WRF_DATA
:
std_logic_vector
(
1
downto
0
)
:
=
"00"
;
constant
c_WRF_OOB
:
std_logic_vector
(
1
downto
0
)
:
=
"01"
;
constant
c_WRF_STATUS
:
std_logic_vector
(
1
downto
0
)
:
=
"10"
;
constant
c_WRF_USER
:
std_logic_vector
(
1
downto
0
)
:
=
"11"
;
constant
c_WRF_OOB_TYPE_RX
:
std_logic_vector
(
3
downto
0
)
:
=
"0000"
;
constant
c_WRF_OOB_TYPE_TX
:
std_logic_vector
(
3
downto
0
)
:
=
"0001"
;
type
t_wrf_status_reg
is
record
is_hp
:
std_logic
;
has_smac
:
std_logic
;
has_crc
:
std_logic
;
error
:
std_logic
;
tag_me
:
std_logic
;
match_class
:
std_logic_vector
(
7
downto
0
);
end
record
;
type
t_wrf_source_out
is
record
adr
:
std_logic_vector
(
1
downto
0
);
dat
:
std_logic_vector
(
15
downto
0
);
cyc
:
std_logic
;
stb
:
std_logic
;
we
:
std_logic
;
sel
:
std_logic_vector
(
1
downto
0
);
end
record
;
type
t_wrf_source_in
is
record
ack
:
std_logic
;
stall
:
std_logic
;
err
:
std_logic
;
rty
:
std_logic
;
end
record
;
type
t_wrf_oob
is
record
valid
:
std_logic
;
oob_type
:
std_logic_vector
(
3
downto
0
);
ts_r
:
std_logic_vector
(
27
downto
0
);
ts_f
:
std_logic_vector
(
3
downto
0
);
frame_id
:
std_logic_vector
(
15
downto
0
);
port_id
:
std_logic_vector
(
5
downto
0
);
end
record
;
subtype
t_wrf_sink_in
is
t_wrf_source_out
;
subtype
t_wrf_sink_out
is
t_wrf_source_in
;
type
t_wrf_source_in_array
is
array
(
natural
range
<>
)
of
t_wrf_source_in
;
type
t_wrf_source_out_array
is
array
(
natural
range
<>
)
of
t_wrf_source_out
;
subtype
t_wrf_sink_in_array
is
t_wrf_source_out_array
;
subtype
t_wrf_sink_out_array
is
t_wrf_source_in_array
;
function
f_marshall_wrf_status
(
stat
:
t_wrf_status_reg
)
return
std_logic_vector
;
function
f_unmarshall_wrf_status
(
stat
:
std_logic_vector
)
return
t_wrf_status_reg
;
constant
c_dummy_src_in
:
t_wrf_source_in
:
=
(
'0'
,
'0'
,
'0'
,
'0'
);
constant
c_dummy_snk_in
:
t_wrf_sink_in
:
=
(
"XX"
,
"XXXXXXXXXXXXXXXX"
,
'0'
,
'0'
,
'0'
,
"XX"
);
end
wr_fabric_pkg
;
package
body
wr_fabric_pkg
is
function
f_marshall_wrf_status
(
stat
:
t_wrf_status_reg
)
return
std_logic_vector
is
variable
tmp
:
std_logic_vector
(
15
downto
0
);
begin
tmp
(
0
)
:
=
stat
.
is_hp
;
tmp
(
1
)
:
=
stat
.
error
;
tmp
(
2
)
:
=
stat
.
has_smac
;
tmp
(
3
)
:
=
stat
.
has_crc
;
tmp
(
15
downto
8
)
:
=
stat
.
match_class
;
return
tmp
;
end
function
;
function
f_unmarshall_wrf_status
(
stat
:
std_logic_vector
)
return
t_wrf_status_reg
is
variable
tmp
:
t_wrf_status_reg
;
begin
tmp
.
is_hp
:
=
stat
(
0
);
tmp
.
error
:
=
stat
(
1
);
tmp
.
has_smac
:
=
stat
(
2
);
tmp
.
has_crc
:
=
stat
(
3
);
tmp
.
match_class
:
=
stat
(
15
downto
8
);
return
tmp
;
end
function
;
end
wr_fabric_pkg
;
hdl/modules/fabric/xwb_fabric_sink.vhd
0 → 100644
View file @
ec013494
-------------------------------------------------------------------------------
-- Title : Wishbone Packet Fabric buffered packet sink
-- Project : WR Cores Collection
-------------------------------------------------------------------------------
-- File : xwb_fabric_sink.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-16
-- Last update: 2012-01-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: A simple WB packet streaming sink with builtin FIFO buffer.
-- Outputs a trivial interface (start-of-packet, end-of-packet, data-valid)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-16 1.0 twlostow Created
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
work
.
genram_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
entity
xwb_fabric_sink
is
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- Wishbone Fabric Interface I/O
snk_i
:
in
t_wrf_sink_in
;
snk_o
:
out
t_wrf_sink_out
;
-- Decoded & buffered fabric
addr_o
:
out
std_logic_vector
(
1
downto
0
);
data_o
:
out
std_logic_vector
(
15
downto
0
);
dvalid_o
:
out
std_logic
;
sof_o
:
out
std_logic
;
eof_o
:
out
std_logic
;
error_o
:
out
std_logic
;
bytesel_o
:
out
std_logic
;
dreq_i
:
in
std_logic
);
end
xwb_fabric_sink
;
architecture
rtl
of
xwb_fabric_sink
is
constant
c_fifo_width
:
integer
:
=
16
+
2
+
4
;
signal
q_valid
,
full
,
we
,
rd
:
std_logic
;
signal
fin
,
fout
,
fout_reg
:
std_logic_vector
(
c_fifo_width
-1
downto
0
);
signal
cyc_d0
,
rd_d0
:
std_logic
;
signal
pre_sof
,
pre_eof
,
pre_bytesel
,
pre_dvalid
:
std_logic
;
signal
post_sof
,
post_dvalid
:
std_logic
;
signal
post_addr
:
std_logic_vector
(
1
downto
0
);
signal
post_data
:
std_logic_vector
(
15
downto
0
);
signal
snk_out
:
t_wrf_sink_out
;
begin
-- rtl
p_delay_cyc_and_rd
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
cyc_d0
<=
'0'
;
rd_d0
<=
'0'
;
else
if
(
full
=
'0'
)
then
cyc_d0
<=
snk_i
.
cyc
;
end
if
;
rd_d0
<=
rd
;
end
if
;
end
if
;
end
process
;
pre_sof
<=
snk_i
.
cyc
and
not
cyc_d0
;
-- sof
pre_eof
<=
not
snk_i
.
cyc
and
cyc_d0
;
-- eof
pre_bytesel
<=
not
snk_i
.
sel
(
0
);
-- bytesel
pre_dvalid
<=
snk_i
.
stb
and
snk_i
.
we
and
snk_i
.
cyc
and
not
snk_out
.
stall
;
-- data valid
fin
(
15
downto
0
)
<=
snk_i
.
dat
;
fin
(
17
downto
16
)
<=
snk_i
.
adr
;
fin
(
21
downto
18
)
<=
pre_sof
&
pre_eof
&
pre_bytesel
&
pre_dvalid
;
snk_out
.
stall
<=
full
or
(
snk_i
.
cyc
and
not
cyc_d0
);
snk_out
.
err
<=
'0'
;
snk_out
.
rty
<=
'0'
;
p_gen_ack
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
snk_out
.
ack
<=
'0'
;
else
snk_out
.
ack
<=
snk_i
.
cyc
and
snk_i
.
stb
and
snk_i
.
we
and
not
snk_out
.
stall
;
end
if
;
end
if
;
end
process
;
snk_o
<=
snk_out
;
we
<=
'1'
when
fin
(
21
downto
18
)
/=
"0000"
and
full
=
'0'
else
'0'
;
rd
<=
q_valid
and
dreq_i
and
not
post_sof
;
U_FIFO
:
generic_shiftreg_fifo
generic
map
(
g_data_width
=>
c_fifo_width
,
g_size
=>
16
)
port
map
(
rst_n_i
=>
rst_n_i
,
clk_i
=>
clk_i
,
d_i
=>
fin
,
we_i
=>
we
,
q_o
=>
fout
,
rd_i
=>
rd
,
almost_full_o
=>
full
,
q_valid_o
=>
q_valid
);
p_fout_reg
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
fout_reg
<=
(
others
=>
'0'
);
elsif
(
rd
=
'1'
)
then
fout_reg
<=
fout
;
end
if
;
end
if
;
end
process
;
post_data
<=
fout_reg
(
15
downto
0
);
post_addr
<=
fout_reg
(
17
downto
16
);
post_sof
<=
fout_reg
(
21
)
and
rd_d0
;
--and q_valid;
post_dvalid
<=
fout_reg
(
18
);
sof_o
<=
post_sof
and
rd_d0
;
dvalid_o
<=
post_dvalid
and
rd_d0
;
error_o
<=
'1'
when
rd_d0
=
'1'
and
(
post_addr
=
c_WRF_STATUS
)
and
(
f_unmarshall_wrf_status
(
post_data
)
.
error
=
'1'
)
else
'0'
;
eof_o
<=
fout_reg
(
20
)
and
rd_d0
;
bytesel_o
<=
fout_reg
(
19
);
data_o
<=
post_data
;
addr_o
<=
post_addr
;
end
rtl
;
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
work
.
genram_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
entity
wb_fabric_sink
is
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
snk_dat_i
:
in
std_logic_vector
(
15
downto
0
);
snk_adr_i
:
in
std_logic_vector
(
1
downto
0
);
snk_sel_i
:
in
std_logic_vector
(
1
downto
0
);
snk_cyc_i
:
in
std_logic
;
snk_stb_i
:
in
std_logic
;
snk_we_i
:
in
std_logic
;
snk_stall_o
:
out
std_logic
;
snk_ack_o
:
out
std_logic
;
snk_err_o
:
out
std_logic
;
snk_rty_o
:
out
std_logic
;
-- Decoded & buffered fabric
addr_o
:
out
std_logic_vector
(
1
downto
0
);
data_o
:
out
std_logic_vector
(
15
downto
0
);
dvalid_o
:
out
std_logic
;
sof_o
:
out
std_logic
;
eof_o
:
out
std_logic
;
error_o
:
out
std_logic
;
bytesel_o
:
out
std_logic
;
dreq_i
:
in
std_logic
);
end
wb_fabric_sink
;
architecture
wrapper
of
wb_fabric_sink
is
component
xwb_fabric_sink
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
snk_i
:
in
t_wrf_sink_in
;
snk_o
:
out
t_wrf_sink_out
;
addr_o
:
out
std_logic_vector
(
1
downto
0
);
data_o
:
out
std_logic_vector
(
15
downto
0
);
dvalid_o
:
out
std_logic
;
sof_o
:
out
std_logic
;
eof_o
:
out
std_logic
;
error_o
:
out
std_logic
;
bytesel_o
:
out
std_logic
;
dreq_i
:
in
std_logic
);
end
component
;
signal
snk_in
:
t_wrf_sink_in
;
signal
snk_out
:
t_wrf_sink_out
;
begin
-- wrapper
U_Wrapped_Sink
:
xwb_fabric_sink
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
rst_n_i
,
snk_i
=>
snk_in
,
snk_o
=>
snk_out
,
addr_o
=>
addr_o
,
data_o
=>
data_o
,
dvalid_o
=>
dvalid_o
,
sof_o
=>
sof_o
,
eof_o
=>
eof_o
,
error_o
=>
error_o
,
bytesel_o
=>
bytesel_o
,
dreq_i
=>
dreq_i
);
snk_in
.
adr
<=
snk_adr_i
;
snk_in
.
dat
<=
snk_dat_i
;
snk_in
.
stb
<=
snk_stb_i
;
snk_in
.
we
<=
snk_we_i
;
snk_in
.
cyc
<=
snk_cyc_i
;
snk_in
.
sel
<=
snk_sel_i
;
snk_stall_o
<=
snk_out
.
stall
;
snk_ack_o
<=
snk_out
.
ack
;
snk_err_o
<=
snk_out
.
err
;
snk_rty_o
<=
snk_out
.
rty
;
end
wrapper
;
hdl/modules/fabric/xwb_fabric_source.vhd
0 → 100644
View file @
ec013494
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
work
.
genram_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
entity
xwb_fabric_source
is
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- Wishbone Fabric Interface I/O
src_i
:
in
t_wrf_source_in
;
src_o
:
out
t_wrf_source_out
;
-- Decoded & buffered fabric
addr_i
:
in
std_logic_vector
(
1
downto
0
);
data_i
:
in
std_logic_vector
(
15
downto
0
);
dvalid_i
:
in
std_logic
;
sof_i
:
in
std_logic
;
eof_i
:
in
std_logic
;
error_i
:
in
std_logic
;
bytesel_i
:
in
std_logic
;
dreq_o
:
out
std_logic
);
end
xwb_fabric_source
;
architecture
rtl
of
xwb_fabric_source
is
constant
c_fifo_width
:
integer
:
=
16
+
2
+
4
;
signal
q_valid
,
full
,
we
,
rd
,
rd_d0
:
std_logic
;
signal
fin
,
fout
:
std_logic_vector
(
c_fifo_width
-1
downto
0
);
signal
pre_dvalid
:
std_logic
;
signal
pre_eof
:
std_logic
;
signal
pre_data
:
std_logic_vector
(
15
downto
0
);
signal
pre_addr
:
std_logic_vector
(
1
downto
0
);
signal
post_dvalid
,
post_eof
,
post_bytesel
,
post_sof
:
std_logic
;
signal
err_status
:
t_wrf_status_reg
;
signal
cyc_int
:
std_logic
;
begin
-- rtl
err_status
.
error
<=
'1'
;
dreq_o
<=
not
full
;
rd
<=
not
src_i
.
stall
;
we
<=
sof_i
or
eof_i
or
error_i
or
dvalid_i
;
pre_dvalid
<=
dvalid_i
or
error_i
;
pre_data
<=
data_i
when
(
error_i
=
'0'
)
else
f_marshall_wrf_status
(
err_status
);
pre_addr
<=
addr_i
when
(
error_i
=
'0'
)
else
c_WRF_STATUS
;
pre_eof
<=
error_i
or
eof_i
;
fin
<=
sof_i
&
pre_eof
&
bytesel_i
&
pre_dvalid
&
pre_addr
&
pre_data
;
U_FIFO
:
generic_shiftreg_fifo
generic
map
(
g_data_width
=>
c_fifo_width
,
g_size
=>
16
)
port
map
(
rst_n_i
=>
rst_n_i
,
clk_i
=>
clk_i
,
d_i
=>
fin
,
we_i
=>
we
,
q_o
=>
fout
,
rd_i
=>
rd
,
almost_full_o
=>
full
,
q_valid_o
=>
q_valid
);
post_sof
<=
fout
(
21
);
post_eof
<=
fout
(
20
);
post_dvalid
<=
fout
(
18
);
p_gen_cyc
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
cyc_int
<=
'0'
;
else
if
(
src_i
.
stall
=
'0'
and
q_valid
=
'1'
)
then
if
(
post_sof
=
'1'
)
then
cyc_int
<=
'1'
;
elsif
(
post_eof
=
'1'
)
then
cyc_int
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
if
;
end
process
;
src_o
.
cyc
<=
cyc_int
or
post_sof
;
src_o
.
we
<=
'1'
;
src_o
.
stb
<=
post_dvalid
and
q_valid
;
src_o
.
sel
<=
'1'
&
not
fout
(
19
);
src_o
.
dat
<=
fout
(
15
downto
0
);
src_o
.
adr
<=
fout
(
17
downto
16
);
end
rtl
;
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
entity
wb_fabric_source
is
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- Wishbone Fabric Interface I/O
src_dat_o
:
out
std_logic_vector
(
15
downto
0
);
src_adr_o
:
out
std_logic_vector
(
1
downto
0
);
src_sel_o
:
out
std_logic_vector
(
1
downto
0
);
src_cyc_o
:
out
std_logic
;
src_stb_o
:
out
std_logic
;
src_we_o
:
out
std_logic
;
src_stall_i
:
in
std_logic
;
src_ack_i
:
in
std_logic
;
src_err_i
:
in
std_logic
;
-- Decoded & buffered fabric
addr_i
:
in
std_logic_vector
(
1
downto
0
);
data_i
:
in
std_logic_vector
(
15
downto
0
);
dvalid_i
:
in
std_logic
;
sof_i
:
in
std_logic
;
eof_i
:
in
std_logic
;
error_i
:
in
std_logic
;
bytesel_i
:
in
std_logic
;
dreq_o
:
out
std_logic
);
end
wb_fabric_source
;
architecture
wrapper
of
wb_fabric_source
is
component
xwb_fabric_source
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
src_i
:
in
t_wrf_source_in
;
src_o
:
out
t_wrf_source_out
;
addr_i
:
in
std_logic_vector
(
1
downto
0
);
data_i
:
in
std_logic_vector
(
15
downto
0
);
dvalid_i
:
in
std_logic
;
sof_i
:
in
std_logic
;
eof_i
:
in
std_logic
;
error_i
:
in
std_logic
;
bytesel_i
:
in
std_logic
;
dreq_o
:
out
std_logic
);
end
component
;
signal
src_in
:
t_wrf_source_in
;
signal
src_out
:
t_wrf_source_out
;
begin
-- wrapper
U_Wrapped_Source
:
xwb_fabric_source
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
rst_n_i
,
src_i
=>
src_in
,
src_o
=>
src_out
,
addr_i
=>
addr_i
,
data_i
=>
data_i
,
dvalid_i
=>
dvalid_i
,
sof_i
=>
sof_i
,
eof_i
=>
eof_i
,
error_i
=>
error_i
,
bytesel_i
=>
bytesel_i
,
dreq_o
=>
dreq_o
);
src_cyc_o
<=
src_out
.
cyc
;
src_stb_o
<=
src_out
.
stb
;
src_we_o
<=
src_out
.
we
;
src_sel_o
<=
src_out
.
sel
;
src_adr_o
<=
src_out
.
adr
;
src_dat_o
<=
src_out
.
dat
;
src_in
.
rty
<=
'0'
;
src_in
.
err
<=
src_err_i
;
src_in
.
ack
<=
src_ack_i
;
src_in
.
stall
<=
src_stall_i
;
end
wrapper
;
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