Skip to content

B
Beam Positoning Monitor - Gateware
Commit eec752da authored by Lucas Russo's avatar Lucas Russo
Browse files
Options

hdl/modules/dbe_wishbone/*: add AFC DIAG debug outputs

parent d696aee8
Hide whitespace changes
Inline Side-by-side
Showing with 57 additions and 2 deletions
hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd
View file @ eec752da
...@@ -1591,6 +1591,13 @@ package dbe_wishbone_pkg is ...@@ -1591,6 +1591,13 @@ package dbe_wishbone_pkg is
wb_rty_o : out std_logic; wb_rty_o : out std_logic;
wb_stall_o : out std_logic; wb_stall_o : out std_logic;
dbg_spi_clk_o : out std_logic;
dbg_spi_valid_o : out std_logic;
dbg_en_o : out std_logic;
dbg_addr_o : out std_logic_vector(7 downto 0);
dbg_serial_data_o : out std_logic_vector(31 downto 0);
dbg_spi_data_o : out std_logic_vector(31 downto 0);
----------------------------- -----------------------------
-- SPI interface -- SPI interface
----------------------------- -----------------------------
...@@ -1622,6 +1629,13 @@ package dbe_wishbone_pkg is ...@@ -1622,6 +1629,13 @@ package dbe_wishbone_pkg is
wb_slv_i : in t_wishbone_slave_in; wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out; wb_slv_o : out t_wishbone_slave_out;
dbg_spi_clk_o : out std_logic;
dbg_spi_valid_o : out std_logic;
dbg_en_o : out std_logic;
dbg_addr_o : out std_logic_vector(7 downto 0);
dbg_serial_data_o : out std_logic_vector(31 downto 0);
dbg_spi_data_o : out std_logic_vector(31 downto 0);
----------------------------- -----------------------------
-- SPI interface -- SPI interface
----------------------------- -----------------------------
......
hdl/modules/dbe_wishbone/wb_afc_diag/spi_link_top.vhd
View file @ eec752da
...@@ -83,7 +83,7 @@ begin ...@@ -83,7 +83,7 @@ begin
byte_sel => spi_byte_sel, byte_sel => spi_byte_sel,
addr_sel => spi_addr_sel, addr_sel => spi_addr_sel,
addr_complete => open, addr_complete => open,
testout => open ); --SPI_testout ); testout => SPI_testout );
--SPI_data_i <= x"12345677"; --SPI_data_i <= x"12345677";
-- SPI_data_i <= intbus; -- SPI_data_i <= intbus;
......
hdl/modules/dbe_wishbone/wb_afc_diag/wb_afc_diag.vhd
View file @ eec752da
...@@ -57,6 +57,13 @@ port ...@@ -57,6 +57,13 @@ port
wb_rty_o : out std_logic; wb_rty_o : out std_logic;
wb_stall_o : out std_logic; wb_stall_o : out std_logic;
dbg_spi_clk_o : out std_logic;
dbg_spi_valid_o : out std_logic;
dbg_en_o : out std_logic;
dbg_addr_o : out std_logic_vector(7 downto 0);
dbg_serial_data_o : out std_logic_vector(31 downto 0);
dbg_spi_data_o : out std_logic_vector(31 downto 0);
----------------------------- -----------------------------
-- SPI interface -- SPI interface
----------------------------- -----------------------------
...@@ -74,7 +81,7 @@ architecture rtl of wb_afc_diag is ...@@ -74,7 +81,7 @@ architecture rtl of wb_afc_diag is
-- General Constants -- General Constants
----------------------------- -----------------------------
constant c_periph_addr_size : natural := 8; constant c_periph_addr_size : natural := 8+2;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Wishbone Adapater Signals -- Wishbone Adapater Signals
...@@ -98,6 +105,13 @@ architecture rtl of wb_afc_diag is ...@@ -98,6 +105,13 @@ architecture rtl of wb_afc_diag is
SPI_SO : out std_logic; SPI_SO : out std_logic;
SPI_CLK : in std_logic; SPI_CLK : in std_logic;
dbg_spi_clk : out std_logic;
dbg_SERIAL_valid : out std_logic;
dbg_en : out std_logic;
dbg_SERIAL_addr : out std_logic_vector(7 downto 0);
dbg_SERIAL_data : out std_logic_vector(31 downto 0);
dbg_SPI_data : out std_logic_vector(31 downto 0);
wb_addr_i : in std_logic_vector(15 downto 0); wb_addr_i : in std_logic_vector(15 downto 0);
wb_data_i : in std_logic_vector(31 downto 0); wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0); wb_data_o : out std_logic_vector(31 downto 0);
...@@ -162,6 +176,13 @@ begin ...@@ -162,6 +176,13 @@ begin
SPI_SO => spi_so, SPI_SO => spi_so,
SPI_CLK => spi_clk, SPI_CLK => spi_clk,
dbg_spi_clk => dbg_spi_clk_o,
dbg_en => dbg_en_o,
dbg_SERIAL_valid => dbg_spi_valid_o,
dbg_SERIAL_addr => dbg_addr_o,
dbg_SERIAL_data => dbg_serial_data_o,
dbg_SPI_data => dbg_spi_data_o,
-- Wishbone bus -- Wishbone bus
wb_addr_i => wb_slv_adp_out.adr(15 downto 0), wb_addr_i => wb_slv_adp_out.adr(15 downto 0),
wb_data_i => wb_slv_adp_out.dat, wb_data_i => wb_slv_adp_out.dat,
...@@ -173,4 +194,10 @@ begin ...@@ -173,4 +194,10 @@ begin
wb_ack_o => wb_slv_adp_in.ack wb_ack_o => wb_slv_adp_in.ack
); );
-- Unused wishbone signals
wb_slv_adp_in.int <= '0';
wb_slv_adp_in.err <= '0';
wb_slv_adp_in.rty <= '0';
wb_slv_adp_in.stall <= '0';
end rtl; end rtl;
hdl/modules/dbe_wishbone/wb_afc_diag/xwb_afc_diag.vhd
View file @ eec752da
...@@ -47,6 +47,13 @@ port ...@@ -47,6 +47,13 @@ port
wb_slv_i : in t_wishbone_slave_in; wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out; wb_slv_o : out t_wishbone_slave_out;
dbg_spi_clk_o : out std_logic;
dbg_spi_valid_o : out std_logic;
dbg_en_o : out std_logic;
dbg_addr_o : out std_logic_vector(7 downto 0);
dbg_serial_data_o : out std_logic_vector(31 downto 0);
dbg_spi_data_o : out std_logic_vector(31 downto 0);
----------------------------- -----------------------------
-- SPI interface -- SPI interface
----------------------------- -----------------------------
...@@ -92,6 +99,13 @@ begin ...@@ -92,6 +99,13 @@ begin
wb_rty_o => wb_slv_o.rty, wb_rty_o => wb_slv_o.rty,
wb_stall_o => wb_slv_o.stall, wb_stall_o => wb_slv_o.stall,
dbg_spi_clk_o => dbg_spi_clk_o,
dbg_spi_valid_o => dbg_spi_valid_o,
dbg_en_o => dbg_en_o,
dbg_addr_o => dbg_addr_o,
dbg_serial_data_o => dbg_serial_data_o,
dbg_spi_data_o => dbg_spi_data_o,
----------------------------- -----------------------------
-- SPI interface -- SPI interface
----------------------------- -----------------------------
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment