testbench/*/wb_acq_core_test/**: add cascaded AXI interconnect to mimic real structure

In our real project we have a cascaded AXI interconnect. So, we mimic this structure here.

testbench/*/wb_acq_core_test/**: add cascaded AXI interconnect to mimic real structure
In our real project we have a cascaded AXI interconnect. So, we mimic this structure here.
f16545e4 · Lucas Russo · 1a226e5d · f16545e4
Commit f16545e4 authored Jan 05, 2016 by Lucas Russo
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wb_acq_core_tb.v ...acq_core_test/verilog/artix7/full_tb_mux/wb_acq_core_tb.v +200 -50

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--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wb_acq_core_tb.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wb_acq_core_tb.v