Skip to content

B
Beam Positoning Monitor - Gateware
Commit f2e69761 authored by Lucas Russo's avatar Lucas Russo
Browse files
Options

modules/*/wb_acq_core/wb_acq_core_plain.vhd: connect generics to top module 

Now g_ddr_interface_type and g_max_burst_size
both are connected to the top level wb_acq_core_plain
module
parent 16dd56a9
Hide whitespace changes
Inline Side-by-side
Showing with 6 additions and 2 deletions
hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core_plain.vhd
View file @ f2e69761
......@@ -47,7 +47,9 @@ generic
g_ddr_addr_width : natural := 32; -- be careful changing these!
g_multishot_ram_size : natural := 2048;
g_fifo_fc_size : natural := 64;
g_sim_readback : boolean := false
g_sim_readback : boolean := false;
g_ddr_interface_type : string := "AXIS";
g_max_burst_size : natural := 4
);
port
(
......@@ -155,7 +157,9 @@ begin
g_ddr_dq_width => g_ddr_dq_width,
g_multishot_ram_size => g_multishot_ram_size,
g_fifo_fc_size => g_fifo_fc_size,
g_sim_readback => g_sim_readback
g_sim_readback => g_sim_readback,
g_ddr_interface_type => g_ddr_interface_type,
g_max_burst_size => g_max_burst_size
)
port map
(
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment