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Beam Positoning Monitor - Gateware
Commit f5419630 authored by Adrian Byszuk's avatar Adrian Byszuk
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Change DDR core refclk to no_buffer. 

Add missing DDR core definition files. Small fixes.
parent 3ac79ee5
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Showing with 458 additions and 41 deletions
hdl/ip_cores/pcie/7k325ffg900/ddr_core/ddr_core.xci
View file @ f5419630
......@@ -9,7 +9,7 @@
<spirit:instanceName>ddr_core</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="mig_7series" spirit:version="2.3"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.XML_INPUT_FILE">mig_a.prj</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.XML_INPUT_FILE">mig_b.prj</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MIG_DONT_TOUCH_PARAM">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BOARD_MIG_PARAM">Custom</spirit:configurableElementValue>
......@@ -21,7 +21,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TEMP_MON_CONTROL">INTERNAL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.POLARITY">ACTIVE_HIGH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IS_CLK_SHARED">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SYSCLK_TYPE">DIFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SYSCLK_TYPE">NOBUF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USE_AXI">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ECC">OFF</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DDR3_DQ_WIDTH">64</spirit:configurableElementValue>
......
hdl/ip_cores/pcie/7k325ffg900/ddr_core/mig_a.prj 0 → 100755
View file @ f5419630
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hdl/ip_cores/pcie/7k325ffg900/ddr_core/mig_b.prj 0 → 100755
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hdl/ip_cores/pcie/7k325ffg900/ipcores_pkg.vhd
View file @ f5419630
......@@ -200,8 +200,7 @@ Port(
ddr3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr3_dm : out STD_LOGIC_VECTOR ( 7 downto 0 );
ddr3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
sys_clk_p : in STD_LOGIC;
sys_clk_n : in STD_LOGIC;
sys_clk_i : in STD_LOGIC;
ui_clk : out STD_LOGIC;
ui_clk_sync_rst : out STD_LOGIC;
mmcm_locked : out STD_LOGIC;
......
hdl/modules/pcie/bpm_pcie.vhd
View file @ f5419630
......@@ -61,11 +61,11 @@ entity bpm_pcie is
pci_exp_txp : out std_logic_vector(c_pcielanes-1 downto 0);
pci_exp_txn : out std_logic_vector(c_pcielanes-1 downto 0);
-- Necessity signals
ddr_sys_clk_p : in std_logic;
ddr_sys_clk_n : in std_logic;
ddr_sys_clk : in std_logic;
ddr_sys_rst : in std_logic;
pci_sys_clk_p : in std_logic; --100 MHz PCIe Clock
pci_sys_clk_n : in std_logic; --100 MHz PCIe Clock
sys_rst_n : in std_logic; --Reset to PCIe core
pci_sys_rst_n : in std_logic; --Reset to PCIe core
-- DDR memory controller interface --
ddr_axi_aclk_o : out std_logic;
ddr_axi_aresetn_o : out std_logic;
......@@ -313,21 +313,14 @@ architecture Behavioral of bpm_pcie is
signal ddr_s2mm_err : std_logic;
signal sys_clk_c : std_logic;
signal sys_reset_n_c : std_logic;
signal sys_reset_c : std_logic;
signal reset_n : std_logic;
signal localId : std_logic_vector(15 downto 0);
signal pcie_link_width : std_logic_vector(5 downto 0);
begin
sys_reset_c <= not sys_reset_n_c;
sys_reset_n_ibuf : IBUF
port map (
O => sys_reset_n_c,
I => sys_rst_n
);
sys_reset_c <= not pci_sys_rst_n;
pcieclk_ibuf : IBUFDS_GTE2
port map (
......@@ -627,7 +620,7 @@ port map(
-- 8. System(SYS) Interface --
-------------------------------------------------------------------------------------------------------------------
sys_clk => sys_clk_c ,
sys_rst_n => sys_reset_n_c
sys_rst_n => pci_sys_rst_n
);
-- ---------------------------------------------------------------
......@@ -831,11 +824,10 @@ DDRs_ctrl_module: entity work.DDR_Transact
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
ddr_sys_clk_p => ddr_sys_clk_p,
ddr_sys_clk_n => ddr_sys_clk_n,
ddr_sys_clk => ddr_sys_clk,
--clocking & reset
pcie_clk => user_clk,
pcie_reset => sys_reset_c
sys_reset => ddr_sys_rst
);
......
hdl/modules/pcie/common/Registers.vhd
View file @ f5419630
......@@ -221,9 +221,11 @@ architecture Behavioral of Regs_Group is
signal Reg_RdMuxer_Hi : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
signal Reg_RdMuxer_Lo : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
-- Event Buffer
-- Event Buffer reset
-- quite a long one because with gen2 speed PCIe user clock is 4 ns
-- so assuming wb_clk = 10 ns we need at least 13 clock cycles to satisfy reset requirements
signal wb_FIFO_Rst_i : std_logic;
signal wb_FIFO_Rst_dly : std_logic_vector(6 downto 0);
signal wb_FIFO_Rst_dly : std_logic_vector(19 downto 0);
-- Downstream DMA registers
signal DMA_ds_PA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
......@@ -1815,7 +1817,7 @@ begin
wb_FIFO_Rst_dly <= (others => '1');
else
wb_FIFO_Rst_i <= or_reduce(wb_FIFO_Rst_dly);
wb_FIFO_Rst_dly <= wb_FIFO_Rst_dly(5 downto 0) & (Regs_WrEn_r2
wb_FIFO_Rst_dly <= wb_FIFO_Rst_dly(18 downto 0) & (Regs_WrEn_r2
and ((Reg_WrMuxer_Hi(CINT_ADDR_EB_STACON) and Command_is_Reset_Hi)
or (Reg_WrMuxer_Lo(CINT_ADDR_EB_STACON) and Command_is_Reset_Lo)));
end if;
......
hdl/modules/pcie/common/ddr_Transact.vhd
View file @ f5419630
......@@ -46,8 +46,7 @@ entity DDR_Transact is
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(C_DDR_DM_WIDTH-1 downto 0);
ddr3_odt : out std_logic_vector(C_DDR_ODT_WIDTH-1 downto 0);
ddr_sys_clk_p : in std_logic;
ddr_sys_clk_n : in std_logic;
ddr_sys_clk : in std_logic;
--AXI4 stream command/data
axis_mm2s_cmd_tvalid : IN STD_LOGIC;
axis_mm2s_cmd_tready : OUT STD_LOGIC;
......@@ -124,7 +123,7 @@ entity DDR_Transact is
--clocking & reset
pcie_clk : in std_logic;
pcie_reset : in std_logic
sys_reset : in std_logic
);
end entity DDR_Transact;
......@@ -133,7 +132,7 @@ architecture Behavioral of DDR_Transact is
-- Signal & type declarations
-- ----------------------------------------------------------------------------
signal ddr_ui_clk, ddr_mmcm_locked : std_logic;
signal ddr_ui_rst, irconnect_arstn, ddr_axi_aresetn, pcie_axi_aresetn, pcie_resetn : std_logic;
signal ddr_ui_rst, irconnect_arstn, ddr_axi_aresetn, pcie_axi_aresetn : std_logic;
signal ddr_axi_awid, ddr_axi_arid, ddr_axi_bid, ddr_axi_rid : std_logic_vector(3 downto 0);
signal pcie_axi_awaddr, ddr_axi_awaddr : std_logic_vector(31 downto 0);
signal pcie_axi_awlen, ddr_axi_awlen : std_logic_vector(7 downto 0);
......@@ -166,8 +165,6 @@ signal pcie_axi_rlast, ddr_axi_rlast : std_logic;
begin
pcie_resetn <= not(pcie_reset);
axi_interconnect_i : axi_interconnect
PORT MAP (
INTERCONNECT_ACLK => ddr_ui_clk,
......@@ -297,7 +294,7 @@ PORT MAP (
m_axi_mm2s_aresetn => pcie_axi_aresetn,
mm2s_err => mm2s_err,
m_axis_mm2s_cmdsts_aclk => pcie_clk,
m_axis_mm2s_cmdsts_aresetn => pcie_resetn,
m_axis_mm2s_cmdsts_aresetn => pcie_axi_aresetn,
s_axis_mm2s_cmd_tvalid => axis_mm2s_cmd_tvalid,
s_axis_mm2s_cmd_tready => axis_mm2s_cmd_tready,
s_axis_mm2s_cmd_tdata => axis_mm2s_cmd_tdata,
......@@ -329,7 +326,7 @@ PORT MAP (
m_axi_s2mm_aresetn => pcie_axi_aresetn,
s2mm_err => s2mm_err,
m_axis_s2mm_cmdsts_awclk => pcie_clk,
m_axis_s2mm_cmdsts_aresetn => pcie_resetn,
m_axis_s2mm_cmdsts_aresetn => pcie_axi_aresetn,
s_axis_s2mm_cmd_tvalid => axis_s2mm_cmd_tvalid,
s_axis_s2mm_cmd_tready => axis_s2mm_cmd_tready,
s_axis_s2mm_cmd_tdata => axis_s2mm_cmd_tdata,
......@@ -441,8 +438,7 @@ begin
s_axi_rvalid => ddr_axi_rvalid,
s_axi_rready => ddr_axi_rready,
-- System Clock Ports
sys_clk_p => ddr_sys_clk_p,
sys_clk_n => ddr_sys_clk_n,
sys_clk_i => ddr_sys_clk,
sys_rst => ddr_sys_rst
);
......@@ -458,7 +454,7 @@ begin
-- This should provide a reliable reset chain where global reset correctly sets up all interfaces
-- and PCIe core or DDR core reset correctly reset all AXI interfaces (as required by Interconnect IP)
ddr_sys_rst <= pcie_reset or ddr_reset;
ddr_sys_rst <= sys_reset or ddr_reset;
irconnect_arstn <= not(ddr_ui_rst) and not(axi_reset);
s_axi_aclk_out <= ddr_ui_clk;
......
hdl/sim/pcie/pci_exp_usrapp_tx.v
View file @ f5419630
......@@ -400,7 +400,7 @@ end
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h0, 4'hF);
TSK_WAIT_FOR_READ_DATA;
if (P_READ_DATA[31:16] != 16'h7014) begin
if (P_READ_DATA[31:16] != 16'h7021) begin
$display("[%t] : Check Device/Vendor ID - FAILED", $realtime);
$display("[%t] : Data Error Mismatch, Parameter Data %x != Read Data %x", $realtime, 16'h7014, P_READ_DATA);
error_check = 1;
......
hdl/syn/pcie/kc705.xdc
View file @ f5419630
......@@ -9,12 +9,22 @@ set_property PACKAGE_PIN G25 [get_ports sys_rst_n]
set_property LOC IBUFDS_GTE2_X0Y1 [get_cells -hier -filter {name=~ */pcieclk_ibuf}]
set_property PACKAGE_PIN AD12 [get_ports ddr_sys_clk_p]
set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr_sys_clk_p]
set_property VCCAUX_IO DONTCARE [get_ports ddr_sys_clk_p]
set_property PACKAGE_PIN AD11 [get_ports ddr_sys_clk_n]
set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr_sys_clk_n]
set_property VCCAUX_IO DONTCARE [get_ports ddr_sys_clk_n]
### Timing constraints
create_clock -name sys_clk -period 10 [get_ports pci_sys_clk_p]
create_clock -name pci_sys_clk -period 10 [get_ports pci_sys_clk_p]
create_clock -name ddr_sys_clk -period 5 [get_ports ddr_sys_clk_p]
set_clock_groups -asynchronous \
-group [get_clocks -include_generated_clocks bpm_pcie_i/pcie_core_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i/TXOUTCLK] \
-group [get_clocks -include_generated_clocks ddr_sys_clk_p]
-group [get_clocks -include_generated_clocks ddr_sys_clk]
set_false_path -from [get_ports sys_rst_n]
......
hdl/testbench/pcie/board.v
View file @ f5419630
......@@ -541,8 +541,8 @@ top # (
)
EP (
// SYS Inteface
.sys_clk_n(ep_sys_clk_n),
.sys_clk_p(ep_sys_clk_p),
.pci_sys_clk_n(ep_sys_clk_n),
.pci_sys_clk_p(ep_sys_clk_p),
.sys_rst_n(sys_rst_n),
.ddr_sys_clk_p(ddr_sys_clk_p),
.ddr_sys_clk_n(ddr_sys_clk_n),
......
hdl/top/pcie/top_k7.vhd
View file @ f5419630
......@@ -46,8 +46,10 @@ end entity top;
architecture arch of top is
signal ddr_sys_clk_i : std_logic;
signal ddr_sys_rst_i : std_logic;
signal ddr_axi_aclk_o : std_logic;
signal sys_rst_n_c : std_logic;
signal wbone_clk : std_logic;
signal wbone_addr : std_logic_vector(31 downto 0);
......@@ -88,11 +90,11 @@ begin
pci_exp_txp => pci_exp_txp,
pci_exp_txn => pci_exp_txn,
-- Necessity signals
ddr_sys_clk_p => ddr_sys_clk_p,
ddr_sys_clk_n => ddr_sys_clk_n,
ddr_sys_clk => ddr_sys_clk_i,
ddr_sys_rst => ddr_sys_rst_i,
pci_sys_clk_p => pci_sys_clk_p,
pci_sys_clk_n => pci_sys_clk_n,
sys_rst_n => sys_rst_n,
pci_sys_rst_n => sys_rst_n_c,
-- DDR memory controller AXI4 interface --
-- Slave interface clock
......@@ -199,6 +201,21 @@ begin
--temporary clock assignment
wbone_clk <= ddr_axi_aclk_o;
sys_reset_n_ibuf: IBUF
port map (
O => sys_rst_n_c,
I => sys_rst_n
);
ddr_sys_rst_i <= not sys_rst_n_c;
ddr_inclk_buf: IBUFGDS
port map(
o => ddr_sys_clk_i,
i => ddr_sys_clk_p,
ib => ddr_sys_clk_n
);
end architecture;
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