hdl/*: update Manifest files

fad488cb · Lucas Russo · fa5ab8e4 · fad488cb · fad488cb · fad488cb
Commit fad488cb authored Mar 28, 2013 by Lucas Russo
6 changed files
--- a/hdl/Manifest.py
+++ b/hdl/Manifest.py
@@ -8,6 +8,7 @@ modules = { "local": [
                "modules/fabric",
                "ip_cores/general-cores",
                "ip_cores/etherbone-core",
+				"ip_cores/dsp-cores",
                "platform/virtex6/chipscope"]
 #     "git" : [
 #     ]

--- a/hdl/platform/virtex6/chipscope/Manifest.py
+++ b/hdl/platform/virtex6/chipscope/Manifest.py
 files = ["icon_1_port/chipscope_icon_1_port.ngc", "icon_2_port/chipscope_icon_2_port.ngc", 
-	"icon_4_port/chipscope_icon_4_port.ngc", "chipscope_ila.ngc"]
+	"icon_4_port/chipscope_icon_4_port.ngc", "ila/chipscope_ila.ngc", "ila/chipscope_ila_8192.ngc"]
--- a/hdl/platform/virtex6/chipscope/chipscope_ila.ngc
+++ b/hdl/platform/virtex6/chipscope/chipscope_ila.ngc
--- a/hdl/platform/virtex6/chipscope/chipscope_ila.vhd
+++ b/hdl/platform/virtex6/chipscope/chipscope_ila.vhd
--- a/hdl/platform/virtex6/chipscope/ila/chipscope_ila_8192.ngc
+++ b/hdl/platform/virtex6/chipscope/ila/chipscope_ila_8192.ngc
--- a/hdl/platform/virtex6/chipscope/ila/chipscope_ila_8192.vhd
+++ b/hdl/platform/virtex6/chipscope/ila/chipscope_ila_8192.vhd
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Xilinx, Inc.
+-- All Rights Reserved
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor     : Xilinx
+-- \   \   \/     Version    : 13.4
+--  \   \         Application: XILINX CORE Generator
+--  /   /         Filename   : chipscope_ila_8192.vhd
+-- /___/   /\     Timestamp  : Wed Mar 27 17:21:28 BRT 2013
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Design Name: VHDL Synthesis Wrapper
+-------------------------------------------------------------------------------
+-- This wrapper is used to integrate with Project Navigator and PlanAhead
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY chipscope_ila_8192 IS
+  port (
+    CONTROL: inout std_logic_vector(35 downto 0);
+    CLK: in std_logic;
+    TRIG0: in std_logic_vector(7 downto 0);
+    TRIG1: in std_logic_vector(31 downto 0);
+    TRIG2: in std_logic_vector(31 downto 0);
+    TRIG3: in std_logic_vector(31 downto 0);
+    TRIG4: in std_logic_vector(31 downto 0));
+END chipscope_ila_8192;
+
+ARCHITECTURE chipscope_ila_8192_a OF chipscope_ila_8192 IS
+BEGIN
+
+END chipscope_ila_8192_a;