- 27 Nov, 2015 1 commit
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Gustavo Bruno authored
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- 30 Oct, 2015 15 commits
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
Now, we need to have a synthesis_info_pkg package with the names as described in the top file.
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Lucas Russo authored
This file needs to be generate on each synthesis. Removing it we assure that we have recently generated it.
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Lucas Russo authored
This should be called before every synthesis. This will be done by executing it on build_bitstream.sh script.
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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- 27 Oct, 2015 1 commit
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Lucas Russo authored
We were selecting the channel to demutiplex without waiting for the valid signal. This could cause the MUX to select the wrong channel and the following logic, e.g., acq_trig module, could misdetect a trigger.
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- 26 Oct, 2015 4 commits
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Lucas Russo authored
With this, we can selection different channels to trigger an acquisition and to acquire data.
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Lucas Russo authored
As we changed the acq_trigger interface in commit 71ad6b18, we update it here.
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Lucas Russo authored
Now, we can trigger a specified channel with another channel. For instance, we can monitor the TBT or FOFB amplitude and trigger an acquisition for the ADC.
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Lucas Russo authored
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- 19 Oct, 2015 5 commits
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Lucas Russo authored
Now, we don't have to use the decimation rate as the clock enable. Instead, we can use a faster CE to improve signal latency. This was possible by the new cordic iterative dsp-cores in commit befc6979e4
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Lucas Russo authored
This is necessary as dsp-cores commit befc6979e4 changed (x)wb_position_calc_core interface
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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- 06 Oct, 2015 1 commit
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Lucas Russo authored
Now, we constraint the position calc CDC FIFOs to the left of the FPGA, spanning 3 clock regions.
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- 05 Oct, 2015 3 commits
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Lucas Russo authored
We were missing a test case in that we had a channel width occupying all of the 128-bits of input. This revealed a bug in that we were not correctly selecting the data_id. See commit 0bb5a7b3.
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Lucas Russo authored
The previous value was just a happy coincidence. In fact, when calculating the start address we need the channel sample size.
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Lucas Russo authored
For channels that occupy a number of FIFOs different than the maximum (e.g., for number of FIFOs equal to 4 with data width of 64 bits, a channel having data width equal to 128 would occupy only 2 FIFOs), the data_id selection was wrong. For a channel occupying 2 FIFOs, the data_id index would always select 4, which is correct for the channel occupying all FIFOs, but wrong for the channel with 2 FIFOs.
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- 03 Oct, 2015 1 commit
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Lucas Russo authored
The correct value is the input CE, which is 2, the ADC CE.
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- 01 Oct, 2015 2 commits
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Lucas Russo authored
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Lucas Russo authored
Now, every time we send a stop command to the FSM, we will stop the FSM, reset the FSM counters and send a reset to all other ACQ cores.
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- 28 Sep, 2015 5 commits
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Lucas Russo authored
This is now possible, as we removed unnecessary area constraints from .xdc file and Vivado 2015.2 possible fixes a bug in that the synthesis would get stuck with flatten_hierarchy=rebuild option.
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Lucas Russo authored
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Lucas Russo authored
We were getting the clock name using a hierarchical approach, which could lead to a non-found net, as sometimes cross boundary optimizations are performed (such as when using Vivado option flatten hierarchy)
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Lucas Russo authored
This helps the FC FIFO not to overflow on long DDR3 stalls.
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Lucas Russo authored
This helps debugging issues with the FC fifo.
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- 22 Sep, 2015 2 commits
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Lucas Russo authored
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Lucas Russo authored
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